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ciniml / pin_table.md
Created November 21, 2022 06:37
RMII TangNano9K pin table
名称 ピン 信号名 TN9K FPGAピン
TX1 1 rmii_txd[1] J5 1 38
NC 2
TX-EN 3 rmii_txen J5 2 37
TX0 4 rmii_txd[0] J5 3 36
RX0 5 rmii_rxd[0] J5 4 39
RX1 6 rmii_rxd[1] J5 5 25
REFCLK 7 rmii_txclk J5 6 26
CRS 8 rmii_crs_dv J5 7 27
@ciniml
ciniml / 99-gowin-gwu2x.rules
Created April 16, 2022 18:38
GWU2X GOWIN USB Dongle udev rule
SUBSYSTEMS=="usb", ATTRS{idVendor}=="33aa", ATTRS{idProduct}=="0120", GROUP="plugdev", MODE="0660"
@ciniml
ciniml / Panel_M5HDMI_FS.h
Last active March 27, 2022 02:07
AtomDisplay Precompiled FPGA bistream for M5GFX
This file has been truncated, but you can view the full file.
static constexpr const unsigned char fs_bitstream_rle[] = {
0x16, 0xff, 0x00, 0x03, 0xa5, 0xc3, 0x06, 0x03, 0x00, 0x00, 0x05, 0x11, 0x00, 0x48, 0x1b, 0x10,
0x07, 0x00, 0x00, 0x02, 0x51, 0x00, 0x06, 0xff, 0x01, 0x0b, 0x03, 0x00, 0x00, 0x02, 0xd2, 0x00,
0x02, 0xff, 0x04, 0x00, 0x01, 0x12, 0x03, 0x00, 0x00, 0x05, 0x3b, 0x80, 0x04, 0xc8, 0xf0, 0x1a,
0x00, 0x00, 0x05, 0xc0, 0x34, 0x10, 0x00, 0x80, 0x12, 0x00, 0x00, 0x02, 0x03, 0x01, 0x05, 0x00,
0x00, 0x05, 0xc0, 0x34, 0x10, 0x00, 0x80, 0x02, 0x00, 0x00, 0x03, 0x14, 0x03, 0x01, 0x1c, 0x00,
0x00, 0x04, 0x03, 0x41, 0x00, 0x08, 0x13, 0x00, 0x00, 0x04, 0x34, 0x10, 0x00, 0x80, 0x02, 0x00,
0x00, 0x05, 0x0c, 0x03, 0x41, 0x00, 0x08, 0x13, 0x00, 0x00, 0x04, 0x34, 0x10, 0x00, 0x80, 0x03,
0x00, 0x00, 0x04, 0x03, 0x41, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04, 0x34, 0x10, 0x00, 0x80, 0x19,
0x00, 0x01, 0xc0, 0x06, 0x00, 0x01, 0x0c, 0x16, 0x00, 0x00, 0x05, 0xc0, 0x34, 0x10, 0x00, 0x80,
@ciniml
ciniml / pin_table_gen.py
Last active January 16, 2022 05:56
pin_table_gen.py
#!/usr/bin/env python3
import svgwrite
pin_type_colors = {
'gnd': (0x000000, 0xffffff),
'3v3': (0xc00000, 0xffffff),
'5v': (0xc00000, 0xffffff),
'bat': (0xc0c000, 0x000000),
'hpwr': (0xc0a000, 0x000000),
'i2c': (0x003000, 0x000000),
@ciniml
ciniml / code.py
Created June 7, 2021 20:32
Measure voltage, current and power with Circuit Python on RPi Pico
from board import *
from busio import I2C
import struct
import time
i2c = I2C(GP21, GP20)
i2c.try_lock()
vm_address = 0x49
cm_address = 0x48
@ciniml
ciniml / M5Paper.ino
Created November 28, 2020 22:06
M5Paper Storage Benchmark
#include <M5EPD.h>
#include <Free_Fonts.h>
#include <WiFi.h>
#include <lwip/sockets.h>
#include <lwip/netdb.h>
#include <cstdio>
#include <cstdlib>
#include <cstdint>
#include <cstring>
@ciniml
ciniml / erpc_debug_passthrough.ino
Created November 17, 2020 02:02
Wio Terminal RTL8720D UART Transport Passthrough
#include <wiring_private.h>
#define PIN_BLE_SERIAL_X_RX (84ul)
#define PIN_BLE_SERIAL_X_TX (85ul)
#define PAD_BLE_SERIAL_X_RX (SERCOM_RX_PAD_2)
#define PAD_BLE_SERIAL_X_TX (UART_TX_PAD_0)
#define SERCOM_BLE_SERIAL_X sercom0
static Uart rtl_uart(&SERCOM_BLE_SERIAL_X, PIN_BLE_SERIAL_X_RX, PIN_BLE_SERIAL_X_TX, PAD_BLE_SERIAL_X_RX, PAD_BLE_SERIAL_X_TX);
@ciniml
ciniml / fpga-load.dts
Created October 21, 2020 11:14
Device Tree Overlay Sample
/dts-v1/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "fpga.bin";
};
};
};
@ciniml
ciniml / ieee_1800_2017_example_4_initial.sv
Created July 12, 2020 07:55
ieee_1800_2017_example_4_initial
module multiple;
logic a;
initial a = 1;
// The assigned value of the variable is determinate
initial begin
a <= #4 0; // schedules a = 0 at time 4
a <= #4 1; // schedules a = 1 at time 4
end // At time 4, a = 1
endmodule
@ciniml
ciniml / ISRBlink.ino
Last active September 10, 2020 07:30
Wio Terminal TC interrupt sample (separated)