udmabuf_dma_test_design

design_top.tcl

################################################################
# This is a generated script based on design: design_top
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2017.2
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_top_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xc7z020clg400-1
}


# CHANGE DESIGN NAME HERE
set design_name design_top

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

  # Create ports
  set led [ create_bd_port -dir O -from 3 -to 0 led ]

  # Create instance: axi_dma_0, and set properties
  set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
  set_property -dict [ list \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {64} \
CONFIG.c_m_axi_s2mm_data_width {64} \
CONFIG.c_m_axis_mm2s_tdata_width {64} \
CONFIG.c_mm2s_burst_size {8} \
CONFIG.c_sg_include_stscntrl_strm {0} \
 ] $axi_dma_0

  # Create instance: axi_gpio_led, and set properties
  set axi_gpio_led [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_led ]

  # Create instance: axi_smc, and set properties
  set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
  set_property -dict [ list \
CONFIG.NUM_SI {2} \
 ] $axi_smc

  # Create instance: jtag_axi_0, and set properties
  set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ]

  # Create instance: proc_sys_reset_fclk_clk0, and set properties
  set proc_sys_reset_fclk_clk0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_fclk_clk0 ]

  # Create instance: processing_system7_inst, and set properties
  set processing_system7_inst [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_inst ]
  set_property -dict [ list \
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {1} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_S_AXI_ACP {1} \
 ] $processing_system7_inst

  # Create instance: ps7_inst_axi_periph, and set properties
  set ps7_inst_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_inst_axi_periph ]
  set_property -dict [ list \
CONFIG.NUM_MI {2} \
CONFIG.NUM_SI {2} \
 ] $ps7_inst_axi_periph

  # Create instance: system_ila_0, and set properties
  set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.0 system_ila_0 ]
  set_property -dict [ list \
CONFIG.C_INPUT_PIPE_STAGES {1} \
CONFIG.C_MON_TYPE {MIX} \
CONFIG.C_NUM_MONITOR_SLOTS {1} \
CONFIG.C_NUM_OF_PROBES {1} \
CONFIG.C_PROBE0_TYPE {0} \
CONFIG.C_SLOT_0_APC_EN {0} \
CONFIG.C_SLOT_0_AXI_AR_SEL_DATA {1} \
CONFIG.C_SLOT_0_AXI_AR_SEL_TRIG {1} \
CONFIG.C_SLOT_0_AXI_AW_SEL_DATA {1} \
CONFIG.C_SLOT_0_AXI_AW_SEL_TRIG {1} \
CONFIG.C_SLOT_0_AXI_B_SEL_DATA {1} \
CONFIG.C_SLOT_0_AXI_B_SEL_TRIG {1} \
CONFIG.C_SLOT_0_AXI_R_SEL_DATA {1} \
CONFIG.C_SLOT_0_AXI_R_SEL_TRIG {1} \
CONFIG.C_SLOT_0_AXI_W_SEL_DATA {1} \
CONFIG.C_SLOT_0_AXI_W_SEL_TRIG {1} \
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
 ] $system_ila_0

  # Create instance: xlslice_gpio_led, and set properties
  set xlslice_gpio_led [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_gpio_led ]
  set_property -dict [ list \
CONFIG.DIN_FROM {3} \
CONFIG.DOUT_WIDTH {4} \
 ] $xlslice_gpio_led

  # Create interface connections
  connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM]
  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI]
  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI]
  connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins processing_system7_inst/S_AXI_ACP]
connect_bd_intf_net -intf_net [get_bd_intf_nets axi_smc_M00_AXI] [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins system_ila_0/SLOT_0_AXI]
  set_property -dict [ list \
HDL_ATTRIBUTE.DEBUG {true} \
 ] [get_bd_intf_nets axi_smc_M00_AXI]
  connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins ps7_inst_axi_periph/S01_AXI]
  connect_bd_intf_net -intf_net processing_system7_inst_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_inst/DDR]
  connect_bd_intf_net -intf_net processing_system7_inst_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_inst/FIXED_IO]
  connect_bd_intf_net -intf_net processing_system7_inst_M_AXI_GP0 [get_bd_intf_pins processing_system7_inst/M_AXI_GP0] [get_bd_intf_pins ps7_inst_axi_periph/S00_AXI]
  connect_bd_intf_net -intf_net ps7_inst_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_led/S_AXI] [get_bd_intf_pins ps7_inst_axi_periph/M00_AXI]
  connect_bd_intf_net -intf_net ps7_inst_axi_periph_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins ps7_inst_axi_periph/M01_AXI]

  # Create port connections
  connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins processing_system7_inst/IRQ_F2P] [get_bd_pins system_ila_0/probe0]
  set_property -dict [ list \
HDL_ATTRIBUTE.DEBUG {true} \
 ] [get_bd_nets axi_dma_0_s2mm_introut]
  connect_bd_net -net axi_gpio_led_gpio_io_o [get_bd_pins axi_gpio_led/gpio_io_o] [get_bd_pins xlslice_gpio_led/Din]
  connect_bd_net -net proc_sys_reset_fclk_clk0_interconnect_aresetn [get_bd_pins proc_sys_reset_fclk_clk0/interconnect_aresetn] [get_bd_pins ps7_inst_axi_periph/ARESETN]
  connect_bd_net -net proc_sys_reset_fclk_clk0_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_gpio_led/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_fclk_clk0/peripheral_aresetn] [get_bd_pins ps7_inst_axi_periph/M00_ARESETN] [get_bd_pins ps7_inst_axi_periph/M01_ARESETN] [get_bd_pins ps7_inst_axi_periph/S00_ARESETN] [get_bd_pins ps7_inst_axi_periph/S01_ARESETN] [get_bd_pins system_ila_0/resetn]
  connect_bd_net -net processing_system7_inst_FCLK_CLK0 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_gpio_led/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins proc_sys_reset_fclk_clk0/slowest_sync_clk] [get_bd_pins processing_system7_inst/FCLK_CLK0] [get_bd_pins processing_system7_inst/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_inst/S_AXI_ACP_ACLK] [get_bd_pins ps7_inst_axi_periph/ACLK] [get_bd_pins ps7_inst_axi_periph/M00_ACLK] [get_bd_pins ps7_inst_axi_periph/M01_ACLK] [get_bd_pins ps7_inst_axi_periph/S00_ACLK] [get_bd_pins ps7_inst_axi_periph/S01_ACLK] [get_bd_pins system_ila_0/clk]
  connect_bd_net -net processing_system7_inst_FCLK_RESET0_N [get_bd_pins proc_sys_reset_fclk_clk0/ext_reset_in] [get_bd_pins processing_system7_inst/FCLK_RESET0_N]
  connect_bd_net -net xlslice_0_Dout [get_bd_ports led] [get_bd_pins xlslice_gpio_led/Dout]

  # Create address segments
  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_inst/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_inst_ACP_DDR_LOWOCM
  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_inst/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_inst_ACP_DDR_LOWOCM
  create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_gpio_led/S_AXI/Reg] SEG_axi_gpio_led_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7_inst/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_inst/Data] [get_bd_addr_segs axi_gpio_led/S_AXI/Reg] SEG_axi_gpio_led_Reg

  # Exclude Address Segments
  create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_inst/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_inst_ACP_M_AXI_GP0
  exclude_bd_addr_seg [get_bd_addr_segs axi_dma_0/Data_MM2S/SEG_processing_system7_inst_ACP_M_AXI_GP0]

  create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_inst/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_inst_ACP_M_AXI_GP0
  exclude_bd_addr_seg [get_bd_addr_segs axi_dma_0/Data_S2MM/SEG_processing_system7_inst_ACP_M_AXI_GP0]



  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""