gistfile1.txt

//Process started
reg started;
	 
//////////////
// States
// 	0: 	  load
// 	1: 	  start bit
// 	2..8:   data
// 	9: 	  parity bit
// 	10..11: stop bits
//////////////
reg [3:0] state;

always @ (posedge clk) begin
	if(rst) begin
		state <= 4'b0;
		started <= 0;
	end
	else if(start)
		started <= start;
		
	if(ce & shr_load & started) begin
		state <= 1;
		started <= 0;
	end
	else if(ce & state == 11)
		state <= 4'b0;
	else if(shr_ce)
		state <= state + 1;
end