rategen.v

module rategen(
    input clk,
    input rst,
    output cy
    );

reg [25:0] cntr;

assign cy = (cntr == 4);
//assign cy = (cntr == 49999999);

always @ (posedge clk)
begin
	if( rst | cy )
		cntr <= 0;
	else
		cntr <= cntr + 1;
end

endmodule