7seg_shr.v

module shr_4(
    input clk,
    input ce,
    input rst,
    output [3:0] out
    );

reg [3:0] shr;

assign out = shr;

always @ (posedge clk)
	if(rst)
		shr <= 4'b1110;
	else if(ce)
		shr <= {shr[2:0],shr[3]};
		
endmodule