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@patrickroberts
patrickroberts / alu32.v
Created December 23, 2017 18:54
Recursive ALU module in Verilog HDL
`timescale 1ns / 1ps
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
@justecorruptio
justecorruptio / 2048.py
Last active September 22, 2017 05:17
Tiny 2048
import os,tty;tty.setcbreak(0);M=['']*16
def G(v):
p=['']*4;u=list(filter(str,v));i=3
while u:z=u.pop();p[i]=u and z==u[-1]and 2*u.pop()or z;i-=1
return p
def Y(M,k):i=1;M=zip(*[iter(M)]*4);exec'M=map([list,G][i*k==k*k],zip(*M))[::-1];i+=1;'*4;return sum(M,[])
while 1:
r=id(M)%71+17
while M[r%16]*r:r-=1
if r:M[r%16]=r%7%2*2+2