Skip to content

Instantly share code, notes, and snippets.

@dadeba
Created March 28, 2018 20:31
Embed
What would you like to do?
VHDL FP32
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pipeline_top is
port (
xi : in std_logic_vector(31 downto 0);
yi : in std_logic_vector(31 downto 0);
zi : in std_logic_vector(31 downto 0);
e2 : in std_logic_vector(31 downto 0);
xj : in std_logic_vector(31 downto 0);
yj : in std_logic_vector(31 downto 0);
zj : in std_logic_vector(31 downto 0);
mj : in std_logic_vector(31 downto 0);
ax : out std_logic_vector(31 downto 0);
ay : out std_logic_vector(31 downto 0);
az : out std_logic_vector(31 downto 0);
ap : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end pipeline_top;
architecture source of pipeline_top is
component fp_add_32_23_8_4
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component delay_32_16
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component fp_mul_32_23_8_4
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component delay_32_4
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component delay_32_32
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component fp_sub_32_23_8_4
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component fp_powm12_32_23_8_8
port (
x : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component delay_32_28
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
signal tmp_xxx_5 : std_logic_vector(31 downto 0);
signal tmp_xxx_6 : std_logic_vector(31 downto 0);
signal r3im : std_logic_vector(31 downto 0);
signal r1im : std_logic_vector(31 downto 0);
signal tmp_xxx_4 : std_logic_vector(31 downto 0);
signal tmp_xxx_3 : std_logic_vector(31 downto 0);
signal tmp_xxx_2 : std_logic_vector(31 downto 0);
signal tmp_xxx_1 : std_logic_vector(31 downto 0);
signal tmp_xxx_0 : std_logic_vector(31 downto 0);
signal dy : std_logic_vector(31 downto 0);
signal dx : std_logic_vector(31 downto 0);
signal dz : std_logic_vector(31 downto 0);
signal dx_d_32 : std_logic_vector(31 downto 0);
signal r2i : std_logic_vector(31 downto 0);
signal dy_d_32 : std_logic_vector(31 downto 0);
signal e2_d_16 : std_logic_vector(31 downto 0);
signal dz_d_32 : std_logic_vector(31 downto 0);
signal r1i : std_logic_vector(31 downto 0);
signal r2 : std_logic_vector(31 downto 0);
signal mj_d_28 : std_logic_vector(31 downto 0);
signal tmp_xxx_3_d_4 : std_logic_vector(31 downto 0);
signal pclk : std_logic;
begin
pclk <= clk;
tmp_xxx_5 <= "10111111100000000000000000000000";
unit0 : fp_sub_32_23_8_4 port map (x => zj, y => zi, z => dz, clk => pclk);
unit1 : fp_sub_32_23_8_4 port map (x => xj, y => xi, z => dx, clk => pclk);
unit2 : fp_sub_32_23_8_4 port map (x => yj, y => yi, z => dy, clk => pclk);
unit3 : fp_mul_32_23_8_4 port map (x => dz, y => dz, z => tmp_xxx_3, clk => pclk);
unit4 : fp_mul_32_23_8_4 port map (x => dy, y => dy, z => tmp_xxx_1, clk => pclk);
unit5 : fp_mul_32_23_8_4 port map (x => dx, y => dx, z => tmp_xxx_0, clk => pclk);
unit6 : fp_add_32_23_8_4 port map (x => tmp_xxx_0, y => tmp_xxx_1, z => tmp_xxx_2, clk => pclk);
unit7 : delay_32_4 port map (i => tmp_xxx_3, o => tmp_xxx_3_d_4, clk => pclk);
unit8 : fp_add_32_23_8_4 port map (x => tmp_xxx_2, y => tmp_xxx_3_d_4, z => tmp_xxx_4, clk => pclk);
unit9 : delay_32_16 port map (i => e2, o => e2_d_16, clk => pclk);
unit10 : fp_add_32_23_8_4 port map (x => tmp_xxx_4, y => e2_d_16, z => r2, clk => pclk);
unit11 : fp_powm12_32_23_8_8 port map (x => r2, z => r1i, clk => pclk);
unit12 : fp_mul_32_23_8_4 port map (x => r1i, y => r1i, z => r2i, clk => pclk);
unit13 : delay_32_28 port map (i => mj, o => mj_d_28, clk => pclk);
unit14 : fp_mul_32_23_8_4 port map (x => r1i, y => mj_d_28, z => r1im, clk => pclk);
unit15 : fp_mul_32_23_8_4 port map (x => r1im, y => r2i, z => r3im, clk => pclk);
unit16 : delay_32_32 port map (i => dx, o => dx_d_32, clk => pclk);
unit17 : fp_mul_32_23_8_4 port map (x => r3im, y => dx_d_32, z => ax, clk => pclk);
unit18 : delay_32_32 port map (i => dy, o => dy_d_32, clk => pclk);
unit19 : fp_mul_32_23_8_4 port map (x => r3im, y => dy_d_32, z => ay, clk => pclk);
unit20 : delay_32_32 port map (i => dz, o => dz_d_32, clk => pclk);
unit21 : fp_mul_32_23_8_4 port map (x => r3im, y => dz_d_32, z => az, clk => pclk);
unit22 : fp_mul_32_23_8_4 port map (x => tmp_xxx_5, y => r1im, z => tmp_xxx_6, clk => pclk);
unit23 : delay_32_4 port map (i => tmp_xxx_6, o => ap, clk => pclk);
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity table_powm12_23 is
port (
ind : in std_logic_vector(7 downto 0);
c0 : out std_logic_vector(25 downto 0);
c1 : out std_logic_vector(25 downto 0);
c2 : out std_logic_vector(25 downto 0)
);
end table_powm12_23;
architecture source of table_powm12_23 is
type rom is array(0 to 47) of std_logic_vector(25 downto 0);
constant rom0 : rom := (
"11101100011001001111110000",
"11100101100010001101111100",
"11011111001111010101100100",
"11011001011011111001100000",
"11010100000100000000110101",
"11001111000100011011101100",
"11001010011010011011000001",
"11000110000011101010001001",
"11000001111110001001111010",
"10111110001000001100110100",
"10111010100000010011111100",
"10110111000101001100101000",
"10110011110101101110011101",
"10110000110000111001101011",
"10101101110101110101111010",
"10101011000011110001001000",
"10101000011001111110101101",
"10100101110111110110110001",
"10100011011100110101011101",
"10100001001000011010100010",
"10011110111010001000110101",
"10011100110001100101111101",
"10011010101110011001111010",
"10011000110000001110110111",
"10010110110110110000110101",
"10010101000001101101100110",
"10010011010000110100011011",
"10010001100011110101111001",
"10001111111010100011110111",
"10001110010100110001001111",
"10001100110010010001111110",
"10001011010010111010110111",
"10001001110110100001100001",
"10001000011100111100010101",
"10000111000110000010010100",
"10000101110001101011001000",
"10000100011111101110111110",
"10000011010000000110100100",
"10000010000010101011000110",
"10000000110111010110001100",
"01111111101110000001111000",
"01111110100110101000100001",
"01111101100001000100110110",
"01111100011101010001111001",
"01111011011011001010111111",
"01111010011010101011101101",
"01111001011011101111111000",
"01111000011110010011100111"
);
constant rom1 : rom := (
"10011000110111101101001000",
"10001011111100101000001001",
"10000000101111111000000011",
"01110110111101111000110111",
"01101110010111010110010100",
"01100110110000000111000010",
"01011111111110011011100001",
"01011001111010011010011100",
"01010100011101100110010111",
"01001111100010101010001100",
"01001011000101001010001011",
"01000111000001011000100111",
"01000011010100001101000000",
"00111111111010111101001110",
"00111100110011011000000001",
"00111001111011100000101110",
"00110111010001101011110101",
"00110100110100011100001000",
"00110010100010100000100011",
"00110000011010110010001001",
"00101110011100010010101110",
"00101100100110001011011111",
"00101010110111101011111111",
"00101001010000001001010001",
"00100111101110111101001001",
"00100110010011100101100001",
"00100100111101100011111000",
"00100011101100011100111000",
"00100010011111110111111001",
"00100001010111011110110000",
"00100000010010111101011000",
"00011111010010000001101000",
"00011110010100011011000000",
"00011101011001111010100000",
"00011100100010010010011111",
"00011011101101010110011101",
"00011010111010111011000000",
"00011010001010110101101010",
"00011001011100111100110111",
"00011000110001000111110000",
"00011000000111001110001110",
"00010111011111001000110010",
"00010110111000110000100001",
"00010110010011111111000010",
"00010101110000101110011010",
"00010101001110111001001000",
"00010100101110011010001000",
"00010100001111001100101011"
);
constant rom2 : rom := (
"00101100011110011100001110",
"00100110011000111000100100",
"00100001011010000100111001",
"00011101010010010100001111",
"00011001110101111101011011",
"00010110111100001111001100",
"00010100011110011100111101",
"00010010010111011011001100",
"00010000100011000110100010",
"00001110111110010001111011",
"00001101100110011001101001",
"00001100011001011001110100",
"00001011010101100111011000",
"00001010011001101010101100",
"00001001100100011011100010",
"00001000110100111110000000",
"00001000001010100000000111",
"00000111100100010111110110",
"00000111000010000001110100",
"00000110100010111111111100",
"00000110000110111000100110",
"00000101101101010101110111",
"00000101010110000100110111",
"00000101000000110101010100",
"00000100101101011001000110",
"00000100011011100011111010",
"00000100001011001011000100",
"00000011111100000101001011",
"00000011101110001001111110",
"00000011100001010010001100",
"00000011010101010111011011",
"00000011001010010011111111",
"00000011000000000010110011",
"00000010110110011111011001",
"00000010101101100101101111",
"00000010100101010010001110",
"00000010011101100001101001",
"00000010010110010001000110",
"00000010001111011101111110",
"00000010001001000101111011",
"00000010000011000110110100",
"00000001111101011110101111",
"00000001111000001011111010",
"00000001110011001100110001",
"00000001101110011111110111",
"00000001101010000011111000",
"00000001100101110111100110",
"00000001100001111001111100"
);
begin
c0 <= rom0(CONV_INTEGER(ind));
c1 <= rom1(CONV_INTEGER(ind));
c2 <= rom2(CONV_INTEGER(ind));
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_lshift_27_8_0 is
port (
ss : in std_logic_vector(7 downto 0);
i : in std_logic_vector(26 downto 0);
o : out std_logic_vector(26 downto 0)
);
end int_lshift_27_8_0;
architecture source of int_lshift_27_8_0 is
begin
with ss select
o <= i(26 downto 0) when "00000000", -- 0
i(25 downto 0)&"0" when "00000001", -- 1
i(24 downto 0)&"00" when "00000010", -- 2
i(23 downto 0)&"000" when "00000011", -- 3
i(22 downto 0)&"0000" when "00000100", -- 4
i(21 downto 0)&"00000" when "00000101", -- 5
i(20 downto 0)&"000000" when "00000110", -- 6
i(19 downto 0)&"0000000" when "00000111", -- 7
i(18 downto 0)&"00000000" when "00001000", -- 8
i(17 downto 0)&"000000000" when "00001001", -- 9
i(16 downto 0)&"0000000000" when "00001010", -- 10
i(15 downto 0)&"00000000000" when "00001011", -- 11
i(14 downto 0)&"000000000000" when "00001100", -- 12
i(13 downto 0)&"0000000000000" when "00001101", -- 13
i(12 downto 0)&"00000000000000" when "00001110", -- 14
i(11 downto 0)&"000000000000000" when "00001111", -- 15
i(10 downto 0)&"0000000000000000" when "00010000", -- 16
i(9 downto 0)&"00000000000000000" when "00010001", -- 17
i(8 downto 0)&"000000000000000000" when "00010010", -- 18
i(7 downto 0)&"0000000000000000000" when "00010011", -- 19
i(6 downto 0)&"00000000000000000000" when "00010100", -- 20
i(5 downto 0)&"000000000000000000000" when "00010101", -- 21
i(4 downto 0)&"0000000000000000000000" when "00010110", -- 22
i(3 downto 0)&"00000000000000000000000" when "00010111", -- 23
i(2 downto 0)&"000000000000000000000000" when "00011000", -- 24
i(1 downto 0)&"0000000000000000000000000" when "00011001", -- 25
i(0)&"00000000000000000000000000" when others; -- 26
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_29_3 is
port (
i : in std_logic_vector(28 downto 0);
o : out std_logic_vector(28 downto 0);
clk : in std_logic
);
end delay_29_3;
architecture source of delay_29_3 is
signal dummy1 : std_logic_vector(28 downto 0);
signal dummy2 : std_logic_vector(28 downto 0);
signal dummy3 : std_logic_vector(28 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp_addtest_32_23_8_0 is
port (
tmp : in std_logic_vector(27 downto 0);
exp : in std_logic_vector(7 downto 0);
r1 : in std_logic;
r2 : in std_logic;
r3 : in std_logic;
res : out std_logic_vector(23 downto 0);
expz : out std_logic_vector(7 downto 0);
ulp : out std_logic;
rbit : out std_logic;
sbit : out std_logic;
clk : in std_logic
);
end fp_addtest_32_23_8_0;
architecture source of fp_addtest_32_23_8_0 is
component int_pencx_27_8_0
port (
i : in std_logic_vector(26 downto 0);
ss : out std_logic_vector(7 downto 0)
);
end component;
component int_lshift_27_8_0
port (
ss : in std_logic_vector(7 downto 0);
i : in std_logic_vector(26 downto 0);
o : out std_logic_vector(26 downto 0)
);
end component;
signal res1, res2 : std_logic_vector(23 downto 0);
signal tmp2 : std_logic_vector(26 downto 0);
signal ulp1, rbit1, sbit1 : std_logic;
signal ulp2, rbit2, sbit2 : std_logic;
signal expz1, expz2 : std_logic_vector(7 downto 0);
signal ss : std_logic_vector(7 downto 0);
signal ss_reg : std_logic_vector(7 downto 0);
signal tmp_reg : std_logic_vector(27 downto 0);
signal ulp1_reg : std_logic;
signal rbit1_reg : std_logic;
signal sbit1_reg : std_logic;
signal r3_reg : std_logic;
signal res1_reg : std_logic_vector(23 downto 0);
signal expz1_reg : std_logic_vector(7 downto 0);
signal exp_reg : std_logic_vector(7 downto 0);
begin
-- if res(27) == 1
ulp1 <= tmp(4);
rbit1 <= tmp(3);
sbit1 <= r1 or r2 or r3;
res1 <= tmp(27 downto 4);
expz1 <= exp + '1';
-- else
penc0 : int_pencx_27_8_0 port map(i => tmp(26 downto 0), ss => ss);
process(clk) begin
if(clk'event and clk='1') then
ss_reg <= ss;
tmp_reg <= tmp;
ulp1_reg <= ulp1;
rbit1_reg <= rbit1;
sbit1_reg <= sbit1;
res1_reg <= res1;
expz1_reg <= expz1;
r3_reg <= r3;
exp_reg <= exp;
end if;
end process;
ls0 : int_lshift_27_8_0 port map (ss => ss_reg, i => tmp_reg(26 downto 0), o => tmp2);
ulp2 <= tmp2(3);
rbit2 <= tmp2(2);
sbit2 <= tmp2(1) or r3_reg;
res2 <= tmp2(26 downto 3);
expz2 <= exp_reg - ss_reg;
with tmp_reg(27) select
res <= res1_reg when '1',
res2 when others;
with tmp_reg(27) select
expz <= expz1_reg when '1',
expz2 when others;
with tmp_reg(27) select
ulp <= ulp1_reg when '1',
ulp2 when others;
with tmp_reg(27) select
rbit <= rbit1_reg when '1',
rbit2 when others;
with tmp_reg(27) select
sbit <= sbit1_reg when '1',
sbit2 when others;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_1_7 is
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end delay_1_7;
architecture source of delay_1_7 is
signal dummy1 : std_logic;
signal dummy2 : std_logic;
signal dummy3 : std_logic;
signal dummy4 : std_logic;
signal dummy5 : std_logic;
signal dummy6 : std_logic;
signal dummy7 : std_logic;
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
dummy6 <= dummy5;
o <= dummy6;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_1_2 is
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end delay_1_2;
architecture source of delay_1_2 is
signal dummy1 : std_logic;
signal dummy2 : std_logic;
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
o <= dummy1;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_1_3 is
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end delay_1_3;
architecture source of delay_1_3 is
signal dummy1 : std_logic;
signal dummy2 : std_logic;
signal dummy3 : std_logic;
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp_add_32_23_8_4 is
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end fp_add_32_23_8_4;
architecture source of fp_add_32_23_8_4 is
component extract_32_23_8
port (
x : in std_logic_vector(31 downto 0);
s : out std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0)
);
end component;
component rounding_32_23_8
port (
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
u : in std_logic;
r : in std_logic;
s : in std_logic;
mout : out std_logic_vector(23 downto 0);
eout : out std_logic_vector(7 downto 0)
);
end component;
component compose_32_23_8
port (
s : in std_logic;
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component swap_32
port (
f : in std_logic;
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
xs : out std_logic_vector(31 downto 0);
ys : out std_logic_vector(31 downto 0)
);
end component;
component int_rshift_24_9_0
port (
c : in std_logic_vector(8 downto 0);
i : in std_logic_vector(23 downto 0);
o : out std_logic_vector(27 downto 0)
);
end component;
component int_extractsbit_24_9_0
port (
c : in std_logic_vector(8 downto 0);
i : in std_logic_vector(23 downto 0);
s : out std_logic
);
end component;
component int_sadder_29_2
port (
x : in std_logic_vector(28 downto 0);
sx : in std_logic;
y : in std_logic_vector(28 downto 0);
sy : in std_logic;
z : out std_logic_vector(28 downto 0);
sz : out std_logic;
clk : in std_logic
);
end component;
component fp_addtest_32_23_8_0
port (
tmp : in std_logic_vector(27 downto 0);
exp : in std_logic_vector(7 downto 0);
r1 : in std_logic;
r2 : in std_logic;
r3 : in std_logic;
res : out std_logic_vector(23 downto 0);
expz : out std_logic_vector(7 downto 0);
ulp : out std_logic;
rbit : out std_logic;
sbit : out std_logic;
clk : in std_logic
);
end component;
component underflow_24_8
port (
f : in std_logic;
m1 : in std_logic_vector(23 downto 0);
e1 : in std_logic_vector(7 downto 0);
u1 : in std_logic;
r1 : in std_logic;
s1 : in std_logic;
m2 : in std_logic_vector(23 downto 0);
e2 : in std_logic_vector(7 downto 0);
u2 : in std_logic;
r2 : in std_logic;
s2 : in std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0);
u : out std_logic;
r : out std_logic;
s : out std_logic
);
end component;
component delay_1_2
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end component;
component delay_8_2
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end component;
component delay_1_3
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end component;
component delay_8_3
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end component;
component delay_9_3
port (
i : in std_logic_vector(8 downto 0);
o : out std_logic_vector(8 downto 0);
clk : in std_logic
);
end component;
component delay_24_3
port (
i : in std_logic_vector(23 downto 0);
o : out std_logic_vector(23 downto 0);
clk : in std_logic
);
end component;
signal signz,sz : std_logic;
signal manz,mz : std_logic_vector(23 downto 0);
signal expz,ez : std_logic_vector(7 downto 0);
signal ex0, ey0 : std_logic_vector(8 downto 0);
signal xx, yy : std_logic_vector(31 downto 0);
signal sx, sy : std_logic;
signal mx, my : std_logic_vector(23 downto 0);
signal mx0, my0 : std_logic_vector(23 downto 0);
signal ex, ey : std_logic_vector(7 downto 0);
signal dx : std_logic_vector(8 downto 0);
signal dy : std_logic_vector(8 downto 0);
signal diff : std_logic_vector(8 downto 0);
--
signal res0 : std_logic_vector(23 downto 0);
signal expz0 : std_logic_vector(7 downto 0);
signal signz0 : std_logic;
signal ulp0, rbit0, sbit0 : std_logic;
signal res1 : std_logic_vector(23 downto 0);
signal expz1 : std_logic_vector(7 downto 0);
signal signz1 : std_logic;
signal ulp1, rbit1, sbit1 : std_logic;
--
signal o1 : std_logic_vector(27 downto 0);
signal o2 : std_logic_vector(27 downto 0);
signal r1, r2, r3 : std_logic;
signal a0, a1 : std_logic_vector(28 downto 0);
signal b0, b1 : std_logic_vector(28 downto 0);
signal res : std_logic_vector(28 downto 0);
signal resn : std_logic_vector(28 downto 0);
signal zf : std_logic;
--
signal dd : std_logic_vector(9 downto 0);
signal d0 : std_logic_vector(9 downto 0);
signal manzz : std_logic_vector(23 downto 0);
signal expzz : std_logic_vector(7 downto 0);
signal ulp, rbit, sbit : std_logic;
signal zz : std_logic_vector(31 downto 0);
signal expz0_reg : std_logic_vector(7 downto 0);
signal expz0_regg : std_logic_vector(7 downto 0);
signal r1_reg, r2_reg, r3_reg : std_logic;
signal diff_reg : std_logic_vector(8 downto 0);
signal res0_reg : std_logic_vector(23 downto 0);
signal signz0_reg : std_logic;
signal signz1_reg : std_logic;
signal ulp0_reg, rbit0_reg, sbit0_reg : std_logic;
signal zf_reg : std_logic;
begin
ex0 <= '0'&x(30 downto 23);
ey0 <= '0'&y(30 downto 23);
dx <= ex0 - ey0;
dy <= ey0 - ex0;
-- swap
s0 : swap_32 port map ( f => dx(8), x => x, y => y, xs => xx, ys => yy);
with dx(8) select
diff <= dy when '1',
dx when others;
e0 : extract_32_23_8 port map ( x => xx, s => sx, m => mx0, e => ex);
e1 : extract_32_23_8 port map ( x => yy, s => sy, m => my0, e => ey);
-- if input is zero
with ex select
mx <= (others => '0') when "00000000",
mx0 when others;
with ey select
my <= (others => '0') when "00000000",
my0 when others;
--------------------------------------------------------------------
-- if diff > 24
res0 <= mx;
expz0 <= ex;
signz0 <= sx;
ulp0 <= res0(0);
rbit0 <= '0';
sbit0 <= '1';
-- else
-- o1
o1 <= "00"&mx&"00";
-- o2
shift0 : int_rshift_24_9_0 port map (c => diff, i => my, o => o2);
r1 <= o2(1);
r2 <= o2(0);
-- r3
sb0 : int_extractsbit_24_9_0 port map (c => diff, i => my, s => r3);
----
a0 <= o1(27 downto 0)&'0';
b0 <= o2(27 downto 0)&r3;
--
add: int_sadder_29_2 port map (x => a0, sx => sx, y => b0, sy => sy,
z => resn, sz => signz1, clk => clk);
d1 : delay_1_2 port map (i => r1, o => r1_reg, clk => clk);
d2 : delay_1_2 port map (i => r2, o => r2_reg, clk => clk);
d3 : delay_1_2 port map (i => r3, o => r3_reg, clk => clk);
d4 : delay_8_2 port map (i => expz0, o => expz0_reg, clk => clk);
-- flag zf if res == 0
with resn select
zf <= '1' when "00000000000000000000000000000",
'0' when others;
----
f0 : fp_addtest_32_23_8_0 port map ( tmp => resn(27 downto 0),
exp => expz0_reg, r1 => r1_reg, r2 => r2_reg, r3 => r3_reg,
res => res1, expz => expz1, ulp => ulp1, rbit => rbit1, sbit => sbit1, clk => clk);
process(clk) begin
if(clk'event and clk='1') then
signz1_reg <= signz1;
zf_reg <= zf;
end if;
end process;
--sadd 2 signz1, resn
--test 3 res1, expz1, ulp1, rbit1, sbit1
d5 : delay_1_3 port map (i => signz0, o => signz0_reg, clk => clk);
d6 : delay_1_3 port map (i => ulp0, o => ulp0_reg, clk => clk);
d7 : delay_1_3 port map (i => rbit0, o => rbit0_reg, clk => clk);
d8 : delay_1_3 port map (i => sbit0, o => sbit0_reg, clk => clk);
d9 : delay_8_3 port map (i => expz0, o => expz0_regg, clk => clk);
d10 : delay_9_3 port map (i => diff, o => diff_reg, clk => clk);
d11 : delay_24_3 port map (i => res0, o => res0_reg, clk => clk);
--------------------------------------------------------------------
d0 <= '0'&diff_reg;
dd <= "000011000" - d0;
uf : underflow_24_8 port map (f => dd(8),
m1 => res0_reg, e1 => expz0_regg, u1 => ulp0_reg, r1 => rbit0_reg, s1 => sbit0_reg,
m2 => res1, e2 => expz1, u2 => ulp1, r2 => rbit1, s2 => sbit1,
m => manzz, e => expzz, u => ulp, r => rbit, s => sbit );
with dd(8) select
signz <= signz0_reg when '1',
signz1_reg when others;
r0 : rounding_32_23_8 port map ( m => manzz, e => expzz, u => ulp, r => rbit, s => sbit,
mout => manz, eout=> expz);
with zf_reg select
sz <= signz when '0',
'0' when others;
with zf_reg select
mz <= manz when '0',
"000000000000000000000000" when others;
with zf_reg select
ez <= expz when '0',
"00000000" when others;
c0 : compose_32_23_8 port map (s => sz, m => mz, e => ez, z => z, clk => clk);
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_32_16 is
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end delay_32_16;
architecture source of delay_32_16 is
signal dummy1 : std_logic_vector(31 downto 0);
signal dummy2 : std_logic_vector(31 downto 0);
signal dummy3 : std_logic_vector(31 downto 0);
signal dummy4 : std_logic_vector(31 downto 0);
signal dummy5 : std_logic_vector(31 downto 0);
signal dummy6 : std_logic_vector(31 downto 0);
signal dummy7 : std_logic_vector(31 downto 0);
signal dummy8 : std_logic_vector(31 downto 0);
signal dummy9 : std_logic_vector(31 downto 0);
signal dummy10 : std_logic_vector(31 downto 0);
signal dummy11 : std_logic_vector(31 downto 0);
signal dummy12 : std_logic_vector(31 downto 0);
signal dummy13 : std_logic_vector(31 downto 0);
signal dummy14 : std_logic_vector(31 downto 0);
signal dummy15 : std_logic_vector(31 downto 0);
signal dummy16 : std_logic_vector(31 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
dummy6 <= dummy5;
dummy7 <= dummy6;
dummy8 <= dummy7;
dummy9 <= dummy8;
dummy10 <= dummy9;
dummy11 <= dummy10;
dummy12 <= dummy11;
dummy13 <= dummy12;
dummy14 <= dummy13;
dummy15 <= dummy14;
o <= dummy15;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp_mul_32_23_8_4 is
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end fp_mul_32_23_8_4;
architecture source of fp_mul_32_23_8_4 is
component extract_32_23_8
port (
x : in std_logic_vector(31 downto 0);
s : out std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0)
);
end component;
component rounding_32_23_8
port (
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
u : in std_logic;
r : in std_logic;
s : in std_logic;
mout : out std_logic_vector(23 downto 0);
eout : out std_logic_vector(7 downto 0)
);
end component;
component compose_32_23_8
port (
s : in std_logic;
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component int_mul_24x24_3
port (
x : in std_logic_vector(23 downto 0);
y : in std_logic_vector(23 downto 0);
z : out std_logic_vector(47 downto 0);
clk : in std_logic
);
end component;
component delay_8_3
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end component;
component delay_1_3
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end component;
signal signx, signy, signz, sz : std_logic;
signal manx, many, manz, mz : std_logic_vector(23 downto 0);
signal expx, expy, expz, ez : std_logic_vector(7 downto 0);
signal zerox, zeroy, zero, zero_reg1 : std_logic;
signal bias : std_logic_vector(7 downto 0);
signal res : std_logic_vector(47 downto 0);
signal c : std_logic;
signal res1 : std_logic_vector(23 downto 0);
signal expz0 : std_logic_vector(7 downto 0);
signal expz1 : std_logic_vector(7 downto 0);
signal expzz : std_logic_vector(7 downto 0);
signal ulp, rbit, sbit : std_logic;
signal sbit00 : std_logic_vector(22 downto 0);
signal signz_reg1 : std_logic;
signal expz0_reg1 : std_logic_vector(7 downto 0);
signal expz1_reg1 : std_logic_vector(7 downto 0);
begin
e0 : extract_32_23_8 port map ( x => x, s => signx, m => manx, e => expx);
e1 : extract_32_23_8 port map ( x => y, s => signy, m => many, e => expy);
signz <= signx xor signy;
with expx select
zerox <= '1' when "00000000",
'0' when others;
with expy select
zeroy <= '1' when "00000000",
'0' when others;
zero <= zerox or zeroy;
-- two's complement of bias for exponenet(8 bit)
bias <= "10000001";
-- exponent addtion
expz0 <= expx + expy + bias;
-- for overflow
expz1 <= expz0 + '1';
-- res <= manx * many;
mm : int_mul_24x24_3 port map (x => manx, y => many, z => res, clk => clk);
d1 : delay_8_3 port map (i => expz0, o => expz0_reg1, clk => clk);
d2 : delay_8_3 port map (i => expz1, o => expz1_reg1, clk => clk);
d3 : delay_1_3 port map (i => signz, o => signz_reg1, clk => clk);
d4 : delay_1_3 port map (i => zero, o => zero_reg1, clk => clk);
c <= res(47);
with c select
res1 <= res(47 downto 24) when '1',
res(46 downto 23) when others;
with c select
expzz <= expz1_reg1 when '1',
expz0_reg1 when others;
ulp <= res1(0);
with c select
rbit <= res(23) when '1',
res(22) when others;
with c select
sbit00 <= res(22 downto 0) when '1',
'0'&res(21 downto 0) when others;
with sbit00 select
sbit <= '0' when "00000000000000000000000",
'1' when others;
r0 : rounding_32_23_8 port map ( m => res1, e => expzz, u => ulp, r => rbit, s => sbit,
mout => manz, eout=> expz);
with zero_reg1 select
sz <= signz_reg1 when '0',
'0' when others;
with zero_reg1 select
mz <= manz when '0',
"000000000000000000000000" when others;
with zero_reg1 select
ez <= expz when '0',
"00000000" when others;
c0 : compose_32_23_8 port map (s => sz, m => mz, e => ez, z => z, clk => clk);
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_rshift_24_9_0 is
port (
c : in std_logic_vector(8 downto 0);
i : in std_logic_vector(23 downto 0);
o : out std_logic_vector(27 downto 0)
);
end int_rshift_24_9_0;
architecture source of int_rshift_24_9_0 is
begin
with c select
o <= "00"&i&"00" when "000000000", -- 0
"000"&i&'0' when "000000001", -- 1
"0000"&i when "000000010", -- 2
"00000"&i(23 downto 1) when "000000011", -- 3
"000000"&i(23 downto 2) when "000000100", -- 4
"0000000"&i(23 downto 3) when "000000101", -- 5
"00000000"&i(23 downto 4) when "000000110", -- 6
"000000000"&i(23 downto 5) when "000000111", -- 7
"0000000000"&i(23 downto 6) when "000001000", -- 8
"00000000000"&i(23 downto 7) when "000001001", -- 9
"000000000000"&i(23 downto 8) when "000001010", -- 10
"0000000000000"&i(23 downto 9) when "000001011", -- 11
"00000000000000"&i(23 downto 10) when "000001100", -- 12
"000000000000000"&i(23 downto 11) when "000001101", -- 13
"0000000000000000"&i(23 downto 12) when "000001110", -- 14
"00000000000000000"&i(23 downto 13) when "000001111", -- 15
"000000000000000000"&i(23 downto 14) when "000010000", -- 16
"0000000000000000000"&i(23 downto 15) when "000010001", -- 17
"00000000000000000000"&i(23 downto 16) when "000010010", -- 18
"000000000000000000000"&i(23 downto 17) when "000010011", -- 19
"0000000000000000000000"&i(23 downto 18) when "000010100", -- 20
"00000000000000000000000"&i(23 downto 19) when "000010101", -- 21
"000000000000000000000000"&i(23 downto 20) when "000010110", -- 22
"0000000000000000000000000"&i(23 downto 21) when "000010111", -- 23
"00000000000000000000000000"&i(23 downto 22) when "000011000", -- 24
"000000000000000000000000000"&i(23) when "000011001", -- 25
"0000000000000000000000000000" when others; -- 26
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_mul_24x24_3 is
port (
x : in std_logic_vector(23 downto 0);
y : in std_logic_vector(23 downto 0);
z : out std_logic_vector(47 downto 0);
clk : in std_logic
);
end int_mul_24x24_3;
architecture source of int_mul_24x24_3 is
signal xh : std_logic_vector(11 downto 0);
signal xl : std_logic_vector(11 downto 0);
signal yh : std_logic_vector(11 downto 0);
signal yl : std_logic_vector(11 downto 0);
signal xlyl : std_logic_vector(23 downto 0);
signal xlyh : std_logic_vector(23 downto 0);
signal xhyl : std_logic_vector(23 downto 0);
signal xhyh : std_logic_vector(23 downto 0);
signal xlyl_reg : std_logic_vector(23 downto 0);
signal xlyh_reg : std_logic_vector(23 downto 0);
signal xhyl_reg : std_logic_vector(23 downto 0);
signal xhyh_reg : std_logic_vector(23 downto 0);
signal sumll : std_logic_vector(47 downto 0);
signal sumlh : std_logic_vector(47 downto 0);
signal sumhl : std_logic_vector(47 downto 0);
signal sumhh : std_logic_vector(47 downto 0);
signal sum0 : std_logic_vector(47 downto 0);
signal sum1 : std_logic_vector(47 downto 0);
signal sum0_reg : std_logic_vector(47 downto 0);
signal sum1_reg : std_logic_vector(47 downto 0);
signal res : std_logic_vector(47 downto 0);
begin
xh <= x(23 downto 12);
xl <= x(11 downto 0);
yh <= y(23 downto 12);
yl <= y(11 downto 0);
xlyl <= xl*yl;
xlyh <= xl*yh;
xhyl <= xh*yl;
xhyh <= xh*yh;
process(clk) begin
if(clk'event and clk='1') then
xlyl_reg <= xlyl;
xlyh_reg <= xlyh;
xhyl_reg <= xhyl;
xhyh_reg <= xhyh;
end if;
end process;
-- xy
sumll <= "000000000000000000000000"&xlyl_reg;
sumlh <= "000000000000" & xlyh_reg &"000000000000";
sumhl <= "000000000000" & xhyl_reg &"000000000000";
sumhh <= xhyh_reg&"000000000000000000000000";
sum0 <= sumll+sumlh;
sum1 <= sumhl+sumhh;
process(clk) begin
if(clk'event and clk='1') then
sum0_reg <= sum0;
sum1_reg <= sum1;
end if;
end process;
res <= sum0_reg + sum1_reg;
process(clk) begin
if(clk'event and clk='1') then
z <= res;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity extract_32_23_8 is
port (
x : in std_logic_vector(31 downto 0);
s : out std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0)
);
end extract_32_23_8;
architecture source of extract_32_23_8 is
begin
s <= x(31);
e <= x(30 downto 23);
-- flip a hidden bit
m(23) <= '1';
m(22 downto 0) <= x(22 downto 0);
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_32_4 is
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end delay_32_4;
architecture source of delay_32_4 is
signal dummy1 : std_logic_vector(31 downto 0);
signal dummy2 : std_logic_vector(31 downto 0);
signal dummy3 : std_logic_vector(31 downto 0);
signal dummy4 : std_logic_vector(31 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
o <= dummy3;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_8_7 is
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end delay_8_7;
architecture source of delay_8_7 is
signal dummy1 : std_logic_vector(7 downto 0);
signal dummy2 : std_logic_vector(7 downto 0);
signal dummy3 : std_logic_vector(7 downto 0);
signal dummy4 : std_logic_vector(7 downto 0);
signal dummy5 : std_logic_vector(7 downto 0);
signal dummy6 : std_logic_vector(7 downto 0);
signal dummy7 : std_logic_vector(7 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
dummy6 <= dummy5;
o <= dummy6;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_8_2 is
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end delay_8_2;
architecture source of delay_8_2 is
signal dummy1 : std_logic_vector(7 downto 0);
signal dummy2 : std_logic_vector(7 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
o <= dummy1;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_8_3 is
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end delay_8_3;
architecture source of delay_8_3 is
signal dummy1 : std_logic_vector(7 downto 0);
signal dummy2 : std_logic_vector(7 downto 0);
signal dummy3 : std_logic_vector(7 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_9_3 is
port (
i : in std_logic_vector(8 downto 0);
o : out std_logic_vector(8 downto 0);
clk : in std_logic
);
end delay_9_3;
architecture source of delay_9_3 is
signal dummy1 : std_logic_vector(8 downto 0);
signal dummy2 : std_logic_vector(8 downto 0);
signal dummy3 : std_logic_vector(8 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_interp3_26_23_26_26_7 is
port (
dx : in std_logic_vector(25 downto 0);
c0 : in std_logic_vector(25 downto 0);
c1 : in std_logic_vector(25 downto 0);
c2 : in std_logic_vector(25 downto 0);
z : out std_logic_vector(25 downto 0);
clk : in std_logic
);
end int_interp3_26_23_26_26_7;
architecture source of int_interp3_26_23_26_26_7 is
component int_mul_26x26_3
port (
x : in std_logic_vector(25 downto 0);
y : in std_logic_vector(25 downto 0);
z : out std_logic_vector(51 downto 0);
clk : in std_logic
);
end component;
component delay_26_3
port (
i : in std_logic_vector(25 downto 0);
o : out std_logic_vector(25 downto 0);
clk : in std_logic
);
end component;
component delay_26_6
port (
i : in std_logic_vector(25 downto 0);
o : out std_logic_vector(25 downto 0);
clk : in std_logic
);
end component;
component delay_29_3
port (
i : in std_logic_vector(28 downto 0);
o : out std_logic_vector(28 downto 0);
clk : in std_logic
);
end component;
signal u1 : std_logic_vector(51 downto 0);
signal u1h : std_logic_vector(28 downto 0);
signal u2 : std_logic_vector(51 downto 0);
signal u2h : std_logic_vector(28 downto 0);
signal u2a : std_logic_vector(51 downto 0);
signal u2ah : std_logic_vector(28 downto 0);
signal dx_reg : std_logic_vector(25 downto 0);
signal u1h_reg : std_logic_vector(28 downto 0);
signal c0_reg1 : std_logic_vector(25 downto 0);
signal c0_reg2 : std_logic_vector(25 downto 0);
signal res : std_logic_vector(25 downto 0);
begin
mul0 : int_mul_26x26_3 port map (x => dx, y => c1, z=> u1, clk => clk);
mul1 : int_mul_26x26_3 port map (x => dx, y => c2, z=> u2, clk => clk);
u1h <= u1(51 downto 23);
u2h <= u2(51 downto 23);
mul2 : int_mul_26x26_3 port map (x => dx_reg, y => u2h(25 downto 0), z=> u2a, clk => clk);
u2ah <= u2a(51 downto 23);
d0 : delay_26_3 port map (i => dx, o => dx_reg , clk => clk);
d1 : delay_26_6 port map (i => c0, o => c0_reg2, clk => clk);
d2 : delay_29_3 port map (i => u1h, o => u1h_reg, clk => clk);
res <= c0_reg2 - u1h_reg(25 downto 0) + u2ah(25 downto 0);
process(clk) begin
if(clk'event and clk='1') then
z <= res;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rounding_32_23_8 is
port (
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
u : in std_logic;
r : in std_logic;
s : in std_logic;
mout : out std_logic_vector(23 downto 0);
eout : out std_logic_vector(7 downto 0)
);
end rounding_32_23_8;
architecture source of rounding_32_23_8 is
signal inc : std_logic;
signal eee : std_logic_vector(8 downto 0);
signal res : std_logic_vector(24 downto 0);
begin
inc <= (r and (not s) and u) or (r and s);
res <= ('0'&m) + inc;
with res(24) select
mout <= res(24 downto 1) when '1',
res(23 downto 0) when others;
eee <= ('0'&e) + '1';
with res(24) select
eout <= eee(7 downto 0) when '1',
e when others;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_32_32 is
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end delay_32_32;
architecture source of delay_32_32 is
signal dummy1 : std_logic_vector(31 downto 0);
signal dummy2 : std_logic_vector(31 downto 0);
signal dummy3 : std_logic_vector(31 downto 0);
signal dummy4 : std_logic_vector(31 downto 0);
signal dummy5 : std_logic_vector(31 downto 0);
signal dummy6 : std_logic_vector(31 downto 0);
signal dummy7 : std_logic_vector(31 downto 0);
signal dummy8 : std_logic_vector(31 downto 0);
signal dummy9 : std_logic_vector(31 downto 0);
signal dummy10 : std_logic_vector(31 downto 0);
signal dummy11 : std_logic_vector(31 downto 0);
signal dummy12 : std_logic_vector(31 downto 0);
signal dummy13 : std_logic_vector(31 downto 0);
signal dummy14 : std_logic_vector(31 downto 0);
signal dummy15 : std_logic_vector(31 downto 0);
signal dummy16 : std_logic_vector(31 downto 0);
signal dummy17 : std_logic_vector(31 downto 0);
signal dummy18 : std_logic_vector(31 downto 0);
signal dummy19 : std_logic_vector(31 downto 0);
signal dummy20 : std_logic_vector(31 downto 0);
signal dummy21 : std_logic_vector(31 downto 0);
signal dummy22 : std_logic_vector(31 downto 0);
signal dummy23 : std_logic_vector(31 downto 0);
signal dummy24 : std_logic_vector(31 downto 0);
signal dummy25 : std_logic_vector(31 downto 0);
signal dummy26 : std_logic_vector(31 downto 0);
signal dummy27 : std_logic_vector(31 downto 0);
signal dummy28 : std_logic_vector(31 downto 0);
signal dummy29 : std_logic_vector(31 downto 0);
signal dummy30 : std_logic_vector(31 downto 0);
signal dummy31 : std_logic_vector(31 downto 0);
signal dummy32 : std_logic_vector(31 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
dummy6 <= dummy5;
dummy7 <= dummy6;
dummy8 <= dummy7;
dummy9 <= dummy8;
dummy10 <= dummy9;
dummy11 <= dummy10;
dummy12 <= dummy11;
dummy13 <= dummy12;
dummy14 <= dummy13;
dummy15 <= dummy14;
dummy16 <= dummy15;
dummy17 <= dummy16;
dummy18 <= dummy17;
dummy19 <= dummy18;
dummy20 <= dummy19;
dummy21 <= dummy20;
dummy22 <= dummy21;
dummy23 <= dummy22;
dummy24 <= dummy23;
dummy25 <= dummy24;
dummy26 <= dummy25;
dummy27 <= dummy26;
dummy28 <= dummy27;
dummy29 <= dummy28;
dummy30 <= dummy29;
dummy31 <= dummy30;
o <= dummy31;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_mul_25x27_3 is
port (
x : in std_logic_vector(24 downto 0);
y : in std_logic_vector(26 downto 0);
z : out std_logic_vector(51 downto 0);
clk : in std_logic
);
end int_mul_25x27_3;
architecture source of int_mul_25x27_3 is
signal xh : std_logic_vector(11 downto 0);
signal xl : std_logic_vector(12 downto 0);
signal yh : std_logic_vector(12 downto 0);
signal yl : std_logic_vector(13 downto 0);
signal xlyl : std_logic_vector(26 downto 0);
signal xlyh : std_logic_vector(25 downto 0);
signal xhyl : std_logic_vector(25 downto 0);
signal xhyh : std_logic_vector(24 downto 0);
signal xlyl_reg : std_logic_vector(26 downto 0);
signal xlyh_reg : std_logic_vector(25 downto 0);
signal xhyl_reg : std_logic_vector(25 downto 0);
signal xhyh_reg : std_logic_vector(24 downto 0);
signal sumll : std_logic_vector(51 downto 0);
signal sumlh : std_logic_vector(51 downto 0);
signal sumhl : std_logic_vector(51 downto 0);
signal sumhh : std_logic_vector(51 downto 0);
signal sum0 : std_logic_vector(51 downto 0);
signal sum1 : std_logic_vector(51 downto 0);
signal sum0_reg : std_logic_vector(51 downto 0);
signal sum1_reg : std_logic_vector(51 downto 0);
signal res : std_logic_vector(51 downto 0);
begin
xh <= x(24 downto 13);
xl <= x(12 downto 0);
yh <= y(26 downto 14);
yl <= y(13 downto 0);
xlyl <= xl*yl;
xlyh <= xl*yh;
xhyl <= xh*yl;
xhyh <= xh*yh;
process(clk) begin
if(clk'event and clk='1') then
xlyl_reg <= xlyl;
xlyh_reg <= xlyh;
xhyl_reg <= xhyl;
xhyh_reg <= xhyh;
end if;
end process;
-- xy
sumll <= "0000000000000000000000000"&xlyl_reg;
sumlh <= "000000000000" & xlyh_reg &"00000000000000";
sumhl <= "0000000000000" & xhyl_reg &"0000000000000";
sumhh <= xhyh_reg&"000000000000000000000000000";
sum0 <= sumll+sumlh;
sum1 <= sumhl+sumhh;
process(clk) begin
if(clk'event and clk='1') then
sum0_reg <= sum0;
sum1_reg <= sum1;
end if;
end process;
res <= sum0_reg + sum1_reg;
process(clk) begin
if(clk'event and clk='1') then
z <= res;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_mul_26x26_3 is
port (
x : in std_logic_vector(25 downto 0);
y : in std_logic_vector(25 downto 0);
z : out std_logic_vector(51 downto 0);
clk : in std_logic
);
end int_mul_26x26_3;
architecture source of int_mul_26x26_3 is
signal xh : std_logic_vector(12 downto 0);
signal xl : std_logic_vector(12 downto 0);
signal yh : std_logic_vector(12 downto 0);
signal yl : std_logic_vector(12 downto 0);
signal xlyl : std_logic_vector(25 downto 0);
signal xlyh : std_logic_vector(25 downto 0);
signal xhyl : std_logic_vector(25 downto 0);
signal xhyh : std_logic_vector(25 downto 0);
signal xlyl_reg : std_logic_vector(25 downto 0);
signal xlyh_reg : std_logic_vector(25 downto 0);
signal xhyl_reg : std_logic_vector(25 downto 0);
signal xhyh_reg : std_logic_vector(25 downto 0);
signal sumll : std_logic_vector(51 downto 0);
signal sumlh : std_logic_vector(51 downto 0);
signal sumhl : std_logic_vector(51 downto 0);
signal sumhh : std_logic_vector(51 downto 0);
signal sum0 : std_logic_vector(51 downto 0);
signal sum1 : std_logic_vector(51 downto 0);
signal sum0_reg : std_logic_vector(51 downto 0);
signal sum1_reg : std_logic_vector(51 downto 0);
signal res : std_logic_vector(51 downto 0);
begin
xh <= x(25 downto 13);
xl <= x(12 downto 0);
yh <= y(25 downto 13);
yl <= y(12 downto 0);
xlyl <= xl*yl;
xlyh <= xl*yh;
xhyl <= xh*yl;
xhyh <= xh*yh;
process(clk) begin
if(clk'event and clk='1') then
xlyl_reg <= xlyl;
xlyh_reg <= xlyh;
xhyl_reg <= xhyl;
xhyh_reg <= xhyh;
end if;
end process;
-- xy
sumll <= "00000000000000000000000000"&xlyl_reg;
sumlh <= "0000000000000" & xlyh_reg &"0000000000000";
sumhl <= "0000000000000" & xhyl_reg &"0000000000000";
sumhh <= xhyh_reg&"00000000000000000000000000";
sum0 <= sumll+sumlh;
sum1 <= sumhl+sumhh;
process(clk) begin
if(clk'event and clk='1') then
sum0_reg <= sum0;
sum1_reg <= sum1;
end if;
end process;
res <= sum0_reg + sum1_reg;
process(clk) begin
if(clk'event and clk='1') then
z <= res;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_mul_26x25_3 is
port (
x : in std_logic_vector(25 downto 0);
y : in std_logic_vector(24 downto 0);
z : out std_logic_vector(50 downto 0);
clk : in std_logic
);
end int_mul_26x25_3;
architecture source of int_mul_26x25_3 is
signal xh : std_logic_vector(12 downto 0);
signal xl : std_logic_vector(12 downto 0);
signal yh : std_logic_vector(11 downto 0);
signal yl : std_logic_vector(12 downto 0);
signal xlyl : std_logic_vector(25 downto 0);
signal xlyh : std_logic_vector(24 downto 0);
signal xhyl : std_logic_vector(25 downto 0);
signal xhyh : std_logic_vector(24 downto 0);
signal xlyl_reg : std_logic_vector(25 downto 0);
signal xlyh_reg : std_logic_vector(24 downto 0);
signal xhyl_reg : std_logic_vector(25 downto 0);
signal xhyh_reg : std_logic_vector(24 downto 0);
signal sumll : std_logic_vector(50 downto 0);
signal sumlh : std_logic_vector(50 downto 0);
signal sumhl : std_logic_vector(50 downto 0);
signal sumhh : std_logic_vector(50 downto 0);
signal sum0 : std_logic_vector(50 downto 0);
signal sum1 : std_logic_vector(50 downto 0);
signal sum0_reg : std_logic_vector(50 downto 0);
signal sum1_reg : std_logic_vector(50 downto 0);
signal res : std_logic_vector(50 downto 0);
begin
xh <= x(25 downto 13);
xl <= x(12 downto 0);
yh <= y(24 downto 13);
yl <= y(12 downto 0);
xlyl <= xl*yl;
xlyh <= xl*yh;
xhyl <= xh*yl;
xhyh <= xh*yh;
process(clk) begin
if(clk'event and clk='1') then
xlyl_reg <= xlyl;
xlyh_reg <= xlyh;
xhyl_reg <= xhyl;
xhyh_reg <= xhyh;
end if;
end process;
-- xy
sumll <= "0000000000000000000000000"&xlyl_reg;
sumlh <= "0000000000000" & xlyh_reg &"0000000000000";
sumhl <= "000000000000" & xhyl_reg &"0000000000000";
sumhh <= xhyh_reg&"00000000000000000000000000";
sum0 <= sumll+sumlh;
sum1 <= sumhl+sumhh;
process(clk) begin
if(clk'event and clk='1') then
sum0_reg <= sum0;
sum1_reg <= sum1;
end if;
end process;
res <= sum0_reg + sum1_reg;
process(clk) begin
if(clk'event and clk='1') then
z <= res;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_extractsbit_24_9_0 is
port (
c : in std_logic_vector(8 downto 0);
i : in std_logic_vector(23 downto 0);
s : out std_logic
);
end int_extractsbit_24_9_0;
architecture source of int_extractsbit_24_9_0 is
signal sbits : std_logic_vector(23 downto 0);
begin
with c select
sbits <= "000000000000000000000000" when "000000000", -- 0
"000000000000000000000000" when "000000001", -- 1
"000000000000000000000000" when "000000010", -- 2
"00000000000000000000000"&i(0) when "000000011", -- 3
"0000000000000000000000"&i(1 downto 0) when "000000100", -- 4
"000000000000000000000"&i(2 downto 0) when "000000101", -- 5
"00000000000000000000"&i(3 downto 0) when "000000110", -- 6
"0000000000000000000"&i(4 downto 0) when "000000111", -- 7
"000000000000000000"&i(5 downto 0) when "000001000", -- 8
"00000000000000000"&i(6 downto 0) when "000001001", -- 9
"0000000000000000"&i(7 downto 0) when "000001010", -- 10
"000000000000000"&i(8 downto 0) when "000001011", -- 11
"00000000000000"&i(9 downto 0) when "000001100", -- 12
"0000000000000"&i(10 downto 0) when "000001101", -- 13
"000000000000"&i(11 downto 0) when "000001110", -- 14
"00000000000"&i(12 downto 0) when "000001111", -- 15
"0000000000"&i(13 downto 0) when "000010000", -- 16
"000000000"&i(14 downto 0) when "000010001", -- 17
"00000000"&i(15 downto 0) when "000010010", -- 18
"0000000"&i(16 downto 0) when "000010011", -- 19
"000000"&i(17 downto 0) when "000010100", -- 20
"00000"&i(18 downto 0) when "000010101", -- 21
"0000"&i(19 downto 0) when "000010110", -- 22
"000"&i(20 downto 0) when "000010111", -- 23
"00"&i(21 downto 0) when "000011000", -- 24
"0"&i(22 downto 0) when others; -- 25
with sbits select
s <= '0' when "000000000000000000000000",
'1' when others;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_sadder_29_2 is
port (
x : in std_logic_vector(28 downto 0);
sx : in std_logic;
y : in std_logic_vector(28 downto 0);
sy : in std_logic;
z : out std_logic_vector(28 downto 0);
sz : out std_logic;
clk : in std_logic
);
end int_sadder_29_2;
architecture source of int_sadder_29_2 is
signal flag : std_logic;
signal flag1 : std_logic;
signal flag2 : std_logic;
signal c : std_logic_vector(1 downto 0);
signal c1, c2 : std_logic;
signal c1v, c2v : std_logic_vector(1 downto 0);
signal o1, o2 : std_logic_vector(28 downto 0);
signal res : std_logic_vector(28 downto 0);
signal res0 : std_logic_vector(28 downto 0);
signal resp, resn : std_logic_vector(28 downto 0);
signal zzz : std_logic_vector(28 downto 0);
signal sign0, sign1 : std_logic;
signal o1_reg, o2_reg : std_logic_vector(28 downto 0);
signal c_reg : std_logic_vector(1 downto 0);
signal flag2_reg : std_logic;
begin
flag1 <= sx xor sy;
flag2 <= sx and sy;
with (sx and flag1) select
o1 <= (not x) when '1',
x when others;
with (sx and flag1) select
c1 <= '1' when '1',
'0' when others;
with (sy and flag1) select
o2 <= (not y) when '1',
y when others;
with (sy and flag1) select
c2 <= '1' when '1',
'0' when others;
c1v <= '0'&c1;
c2v <= '0'&c2;
c <= c1v + c2v;
process(clk) begin
if(clk'event and clk='1') then
o1_reg <= o1;
o2_reg <= o2;
c_reg <= c;
flag2_reg <= flag2;
end if;
end process;
-- res <= o1 + o2 + c;
res0 <= o2_reg + c_reg;
res <= o1_reg + res0;
resp <= res;
resn <= (not res) + '1';
sign0 <= res(28);
-- check if res is negative
-- with res(28) select
with sign0 select
zzz <= resn when '1',
resp when others;
-- with res(28) select
-- sign0 <= '1' when '1',
-- '0' when others;
-- sign0 <= res(28);
-- if both inputs are negative
with flag2_reg select
sign1 <= '1' when '1',
sign0 when others;
process(clk) begin
if(clk'event and clk='1') then
sz <= sign1;
z <= zzz;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp_sub_32_23_8_4 is
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end fp_sub_32_23_8_4;
architecture source of fp_sub_32_23_8_4 is
component extract_32_23_8
port (
x : in std_logic_vector(31 downto 0);
s : out std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0)
);
end component;
component rounding_32_23_8
port (
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
u : in std_logic;
r : in std_logic;
s : in std_logic;
mout : out std_logic_vector(23 downto 0);
eout : out std_logic_vector(7 downto 0)
);
end component;
component compose_32_23_8
port (
s : in std_logic;
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component fp_add_32_23_8_4
port (
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
signal signy, signyy : std_logic;
signal many : std_logic_vector(23 downto 0);
signal expy : std_logic_vector(7 downto 0);
signal xx, yy : std_logic_vector(31 downto 0);
begin
xx <= x;
yy(31) <= not y(31);
yy(30 downto 0) <= y(30 downto 0);
fadd : fp_add_32_23_8_4 port map ( x => xx, y => yy, z => z, clk => clk);
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp_powm12_32_23_8_8 is
port (
x : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end fp_powm12_32_23_8_8;
architecture source of fp_powm12_32_23_8_8 is
component extract_32_23_8
port (
x : in std_logic_vector(31 downto 0);
s : out std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0)
);
end component;
component rounding_32_23_8
port (
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
u : in std_logic;
r : in std_logic;
s : in std_logic;
mout : out std_logic_vector(23 downto 0);
eout : out std_logic_vector(7 downto 0)
);
end component;
component compose_32_23_8
port (
s : in std_logic;
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component table_powm12_23
port (
ind : in std_logic_vector(7 downto 0);
c0 : out std_logic_vector(25 downto 0);
c1 : out std_logic_vector(25 downto 0);
c2 : out std_logic_vector(25 downto 0)
);
end component;
component int_interp3_26_23_26_26_7
port (
dx : in std_logic_vector(25 downto 0);
c0 : in std_logic_vector(25 downto 0);
c1 : in std_logic_vector(25 downto 0);
c2 : in std_logic_vector(25 downto 0);
z : out std_logic_vector(25 downto 0);
clk : in std_logic
);
end component;
component underflow_24_8
port (
f : in std_logic;
m1 : in std_logic_vector(23 downto 0);
e1 : in std_logic_vector(7 downto 0);
u1 : in std_logic;
r1 : in std_logic;
s1 : in std_logic;
m2 : in std_logic_vector(23 downto 0);
e2 : in std_logic_vector(7 downto 0);
u2 : in std_logic;
r2 : in std_logic;
s2 : in std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0);
u : out std_logic;
r : out std_logic;
s : out std_logic
);
end component;
component delay_8_7
port (
i : in std_logic_vector(7 downto 0);
o : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end component;
component delay_1_7
port (
i : in std_logic;
o : out std_logic;
clk : in std_logic
);
end component;
signal signx : std_logic;
signal manx : std_logic_vector(23 downto 0);
signal expx : std_logic_vector(7 downto 0);
signal signz : std_logic;
signal manz : std_logic_vector(23 downto 0);
signal expz : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
signal eee : std_logic_vector(7 downto 0);
signal b0 : std_logic_vector(8 downto 0);
signal expx0 : std_logic_vector(8 downto 0);
signal e : std_logic_vector(8 downto 0);
signal ee : std_logic_vector(8 downto 0);
signal eesum : std_logic_vector(8 downto 0);
signal m : std_logic_vector(25 downto 0);
signal base : std_logic_vector(25 downto 0);
signal uuuu : std_logic_vector(25 downto 0);
signal ind : std_logic_vector(7 downto 0);
signal c0 : std_logic_vector(25 downto 0);
signal c1 : std_logic_vector(25 downto 0);
signal c2 : std_logic_vector(25 downto 0);
signal u1 : std_logic_vector(51 downto 0);
signal u1a : std_logic_vector(25 downto 0);
signal u2 : std_logic_vector(51 downto 0);
signal u2a : std_logic_vector(25 downto 0);
signal u2b : std_logic_vector(51 downto 0);
signal u2c : std_logic_vector(25 downto 0);
signal res : std_logic_vector(25 downto 0);
signal manz1 : std_logic_vector(23 downto 0);
signal e1 : std_logic_vector(7 downto 0);
signal ulp1, rbit1, sbit1 : std_logic;
signal manz2 : std_logic_vector(23 downto 0);
signal e2 : std_logic_vector(7 downto 0);
signal ulp2, rbit2, sbit2 : std_logic;
signal manzz : std_logic_vector(23 downto 0);
signal expzz : std_logic_vector(7 downto 0);
signal ulp, rbit, sbit : std_logic;
signal c0_reg : std_logic_vector(25 downto 0);
signal u1a_reg : std_logic_vector(25 downto 0);
signal u1a_reg0 : std_logic_vector(25 downto 0);
signal u2a_reg : std_logic_vector(25 downto 0);
signal u2c_reg : std_logic_vector(25 downto 0);
signal eee_reg : std_logic_vector(7 downto 0);
signal signz_reg : std_logic;
signal m_reg : std_logic_vector(25 downto 0);
begin
signz <= '0';
e0 : extract_32_23_8 port map ( x => x, s => signx, m => manx, e => expx);
b <= "01111111";
expx0 <= '0'&expx;
b0 <= '0'&b;
e <= expx0 - b0;
-- test if exponent is odd
with e(0) select
m <= '0'&manx(23 downto 0)&'0' when '1',
"00"&manx when others;
ee <= '0'&e(8 downto 1);
eesum <= b0 - ee;
eee <= eesum(7 downto 0);
base <= "00100000000000000000000000";
uuuu <= m - base;
ind <= '0'&uuuu(25 downto 19);
table : table_powm12_23 port map ( ind => ind, c0 => c0, c1 => c1, c2 => c2);
interp: int_interp3_26_23_26_26_7 port map ( dx => m, c0 => c0, c1 => c1, c2 => c2, z => res, clk => clk);
d0 : delay_8_7 port map (i => eee, o => eee_reg, clk => clk);
d1 : delay_1_7 port map (i => signz, o => signz_reg, clk => clk);
-- manz1 <= res(25 downto 2);
-- e1 <= eee_reg;
-- ulp1 <= manz1(0);
-- rbit1 <= res(1);
-- sbit1 <= '1';
-- manz2 <= res(24 downto 1);
-- e2 <= eee_reg - '1';
-- ulp2 <= rbit1;
-- rbit2 <= res(0);
-- sbit2 <= '1';
manz1 <= res(24 downto 1);
e1 <= eee_reg - '1';
ulp1 <= manz1(0);
rbit1 <= res(0);
sbit1 <= '1';
manz2 <= res(23 downto 0);
e2 <= eee_reg - "10";
ulp2 <= rbit1;
rbit2 <= '1';
sbit2 <= '1';
uf : underflow_24_8 port map (f => manz1(23),
m1 => manz1, e1 => e1, u1 => ulp1, r1 => rbit1, s1 => sbit1,
m2 => manz2, e2 => e2, u2 => ulp2, r2 => rbit2, s2 => sbit2,
m => manzz, e => expzz, u => ulp, r => rbit, s => sbit );
r0 : rounding_32_23_8 port map ( m => manzz, e => expzz, u => ulp, r => rbit, s => sbit,
mout => manz, eout=> expz);
cc : compose_32_23_8 port map (s => signz_reg, m => manz, e => expz, z => z, clk => clk);
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity underflow_24_8 is
port (
f : in std_logic;
m1 : in std_logic_vector(23 downto 0);
e1 : in std_logic_vector(7 downto 0);
u1 : in std_logic;
r1 : in std_logic;
s1 : in std_logic;
m2 : in std_logic_vector(23 downto 0);
e2 : in std_logic_vector(7 downto 0);
u2 : in std_logic;
r2 : in std_logic;
s2 : in std_logic;
m : out std_logic_vector(23 downto 0);
e : out std_logic_vector(7 downto 0);
u : out std_logic;
r : out std_logic;
s : out std_logic
);
end underflow_24_8;
architecture source of underflow_24_8 is
begin
with f select
m <= m1 when '1',
m2 when others;
with f select
e <= e1 when '1',
e2 when others;
with f select
u <= u1 when '1',
u2 when others;
with f select
r <= r1 when '1',
r2 when others;
with f select
s <= s1 when '1',
s2 when others;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity swap_32 is
port (
f : in std_logic;
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
xs : out std_logic_vector(31 downto 0);
ys : out std_logic_vector(31 downto 0)
);
end swap_32;
architecture source of swap_32 is
begin
with f select
xs <= y when '1',
x when others;
with f select
ys <= x when '1',
y when others;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_24_3 is
port (
i : in std_logic_vector(23 downto 0);
o : out std_logic_vector(23 downto 0);
clk : in std_logic
);
end delay_24_3;
architecture source of delay_24_3 is
signal dummy1 : std_logic_vector(23 downto 0);
signal dummy2 : std_logic_vector(23 downto 0);
signal dummy3 : std_logic_vector(23 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_32_28 is
port (
i : in std_logic_vector(31 downto 0);
o : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end delay_32_28;
architecture source of delay_32_28 is
signal dummy1 : std_logic_vector(31 downto 0);
signal dummy2 : std_logic_vector(31 downto 0);
signal dummy3 : std_logic_vector(31 downto 0);
signal dummy4 : std_logic_vector(31 downto 0);
signal dummy5 : std_logic_vector(31 downto 0);
signal dummy6 : std_logic_vector(31 downto 0);
signal dummy7 : std_logic_vector(31 downto 0);
signal dummy8 : std_logic_vector(31 downto 0);
signal dummy9 : std_logic_vector(31 downto 0);
signal dummy10 : std_logic_vector(31 downto 0);
signal dummy11 : std_logic_vector(31 downto 0);
signal dummy12 : std_logic_vector(31 downto 0);
signal dummy13 : std_logic_vector(31 downto 0);
signal dummy14 : std_logic_vector(31 downto 0);
signal dummy15 : std_logic_vector(31 downto 0);
signal dummy16 : std_logic_vector(31 downto 0);
signal dummy17 : std_logic_vector(31 downto 0);
signal dummy18 : std_logic_vector(31 downto 0);
signal dummy19 : std_logic_vector(31 downto 0);
signal dummy20 : std_logic_vector(31 downto 0);
signal dummy21 : std_logic_vector(31 downto 0);
signal dummy22 : std_logic_vector(31 downto 0);
signal dummy23 : std_logic_vector(31 downto 0);
signal dummy24 : std_logic_vector(31 downto 0);
signal dummy25 : std_logic_vector(31 downto 0);
signal dummy26 : std_logic_vector(31 downto 0);
signal dummy27 : std_logic_vector(31 downto 0);
signal dummy28 : std_logic_vector(31 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
dummy6 <= dummy5;
dummy7 <= dummy6;
dummy8 <= dummy7;
dummy9 <= dummy8;
dummy10 <= dummy9;
dummy11 <= dummy10;
dummy12 <= dummy11;
dummy13 <= dummy12;
dummy14 <= dummy13;
dummy15 <= dummy14;
dummy16 <= dummy15;
dummy17 <= dummy16;
dummy18 <= dummy17;
dummy19 <= dummy18;
dummy20 <= dummy19;
dummy21 <= dummy20;
dummy22 <= dummy21;
dummy23 <= dummy22;
dummy24 <= dummy23;
dummy25 <= dummy24;
dummy26 <= dummy25;
dummy27 <= dummy26;
o <= dummy27;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_addsub_27_1 is
port (
x : in std_logic_vector(26 downto 0);
y : in std_logic_vector(26 downto 0);
f : in std_logic;
z : out std_logic_vector(26 downto 0);
clk : in std_logic
);
end int_addsub_27_1;
architecture source of int_addsub_27_1 is
signal xx, yy : std_logic_vector(26 downto 0);
begin
xx <= x;
with f select
yy <= (not y) when '1',
y when others;
z <= xx + yy + f;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity int_pencx_27_8_0 is
port (
i : in std_logic_vector(26 downto 0);
ss : out std_logic_vector(7 downto 0)
);
end int_pencx_27_8_0;
architecture source of int_pencx_27_8_0 is
begin
process(i) begin
if (i(26) = '1') then
ss <= "00000000";
elsif (i(25) = '1') then
ss <= "00000001";
elsif (i(24) = '1') then
ss <= "00000010";
elsif (i(23) = '1') then
ss <= "00000011";
elsif (i(22) = '1') then
ss <= "00000100";
elsif (i(21) = '1') then
ss <= "00000101";
elsif (i(20) = '1') then
ss <= "00000110";
elsif (i(19) = '1') then
ss <= "00000111";
elsif (i(18) = '1') then
ss <= "00001000";
elsif (i(17) = '1') then
ss <= "00001001";
elsif (i(16) = '1') then
ss <= "00001010";
elsif (i(15) = '1') then
ss <= "00001011";
elsif (i(14) = '1') then
ss <= "00001100";
elsif (i(13) = '1') then
ss <= "00001101";
elsif (i(12) = '1') then
ss <= "00001110";
elsif (i(11) = '1') then
ss <= "00001111";
elsif (i(10) = '1') then
ss <= "00010000";
elsif (i(9) = '1') then
ss <= "00010001";
elsif (i(8) = '1') then
ss <= "00010010";
elsif (i(7) = '1') then
ss <= "00010011";
elsif (i(6) = '1') then
ss <= "00010100";
elsif (i(5) = '1') then
ss <= "00010101";
elsif (i(4) = '1') then
ss <= "00010110";
elsif (i(3) = '1') then
ss <= "00010111";
elsif (i(2) = '1') then
ss <= "00011000";
elsif (i(1) = '1') then
ss <= "00011001";
else
ss <= "00011010";
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compose_32_23_8 is
port (
s : in std_logic;
m : in std_logic_vector(23 downto 0);
e : in std_logic_vector(7 downto 0);
z : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end compose_32_23_8;
architecture source of compose_32_23_8 is
begin
process(clk) begin
if(clk'event and clk='1') then
z(31) <= s;
z(30 downto 23) <= e;
z(22 downto 0) <= m(22 downto 0);
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_26_3 is
port (
i : in std_logic_vector(25 downto 0);
o : out std_logic_vector(25 downto 0);
clk : in std_logic
);
end delay_26_3;
architecture source of delay_26_3 is
signal dummy1 : std_logic_vector(25 downto 0);
signal dummy2 : std_logic_vector(25 downto 0);
signal dummy3 : std_logic_vector(25 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_26_6 is
port (
i : in std_logic_vector(25 downto 0);
o : out std_logic_vector(25 downto 0);
clk : in std_logic
);
end delay_26_6;
architecture source of delay_26_6 is
signal dummy1 : std_logic_vector(25 downto 0);
signal dummy2 : std_logic_vector(25 downto 0);
signal dummy3 : std_logic_vector(25 downto 0);
signal dummy4 : std_logic_vector(25 downto 0);
signal dummy5 : std_logic_vector(25 downto 0);
signal dummy6 : std_logic_vector(25 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
o <= dummy5;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_25_6 is
port (
i : in std_logic_vector(24 downto 0);
o : out std_logic_vector(24 downto 0);
clk : in std_logic
);
end delay_25_6;
architecture source of delay_25_6 is
signal dummy1 : std_logic_vector(24 downto 0);
signal dummy2 : std_logic_vector(24 downto 0);
signal dummy3 : std_logic_vector(24 downto 0);
signal dummy4 : std_logic_vector(24 downto 0);
signal dummy5 : std_logic_vector(24 downto 0);
signal dummy6 : std_logic_vector(24 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
o <= dummy5;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_28_3 is
port (
i : in std_logic_vector(27 downto 0);
o : out std_logic_vector(27 downto 0);
clk : in std_logic
);
end delay_28_3;
architecture source of delay_28_3 is
signal dummy1 : std_logic_vector(27 downto 0);
signal dummy2 : std_logic_vector(27 downto 0);
signal dummy3 : std_logic_vector(27 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_25_3 is
port (
i : in std_logic_vector(24 downto 0);
o : out std_logic_vector(24 downto 0);
clk : in std_logic
);
end delay_25_3;
architecture source of delay_25_3 is
signal dummy1 : std_logic_vector(24 downto 0);
signal dummy2 : std_logic_vector(24 downto 0);
signal dummy3 : std_logic_vector(24 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
o <= dummy2;
end if;
end process;
end source;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay_27_6 is
port (
i : in std_logic_vector(26 downto 0);
o : out std_logic_vector(26 downto 0);
clk : in std_logic
);
end delay_27_6;
architecture source of delay_27_6 is
signal dummy1 : std_logic_vector(26 downto 0);
signal dummy2 : std_logic_vector(26 downto 0);
signal dummy3 : std_logic_vector(26 downto 0);
signal dummy4 : std_logic_vector(26 downto 0);
signal dummy5 : std_logic_vector(26 downto 0);
signal dummy6 : std_logic_vector(26 downto 0);
begin
process(clk) begin
if(clk'event and clk='1') then
dummy1 <= i;
dummy2 <= dummy1;
dummy3 <= dummy2;
dummy4 <= dummy3;
dummy5 <= dummy4;
o <= dummy5;
end if;
end process;
end source;
-------------------------------------------------------------------------------
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment