KiCad DRC rules for JLCPCB, 2 & 4-layer PCB

rules.txt

(version 1)
#Kicad 7

# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
	(constraint track_width (min 5mil))
	(layer outer)
	(condition "A.Type == 'track'"))

(rule "Minimum Trace Spacing (outer layer)"
	(constraint clearance (min 5mil))
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type"))

# 4-layer
(rule "Minimum Trace Width and Spacing (inner layer)"
	(constraint track_width (min 3.5mil))
	(layer inner)
	(condition "A.Type == 'track'"))

(rule "Minimum Trace Spacing (inner layer)"
	(constraint clearance (min 3.5mil))
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type"))

# silkscreen (Kicad 7 only)
(rule "Minimum Text"
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
	(layer "?.Silkscreen"))

(rule "Pad to Silkscreen"
	(constraint silk_clearance (min 0.15mm))
	(layer outer)
	(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

# edge clearance
(rule "Trace to Outline"
	(constraint edge_clearance (min 0.3mm))
	(condition "A.Type == 'track'"))

# This would override board outline and milled areas
#(rule "Trace to V-Cut"
#	(constraint clearance (min 0.4mm))
#	(condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))

# drill/hole size
(rule "drill hole size (mechanical)"
	(constraint hole_size (min 0.2mm) (max 6.3mm)))

(rule "Minimum Via Hole Size"
	(constraint hole_size (min 0.2mm))
	(condition "A.Type == 'via'"))

(rule "Minimum Via Diameter"
	(constraint via_diameter (min 0.45mm))
	(condition "A.Type == 'via'"))

(rule "PTH Hole Size"
	(constraint hole_size (min 0.2mm) (max 6.35mm))
	(condition "A.isPlated()"))

(rule "Minimum Non-plated Hole Size"
	(constraint hole_size (min 0.5mm))
	(condition "A.Type == 'pad' && !A.isPlated()"))
	
(rule "Minimum Castellated Hole Size"
	(constraint hole_size (min 0.6mm))
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))

# clearance
(rule "hole to hole clearance (different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Net != B.Net"))

(rule "via to track clearance"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == 'track'"))

(rule "via to via clearance (same nets)"
	(constraint hole_to_hole (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))

(rule "pad to pad clearance (with hole, different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "pad to pad clearance (without hole, different nets)"
	(constraint clearance (min 0.127mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "NPTH to Track clearance)"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))

(rule "PTH to Track clearance)"
	(constraint hole_clearance (min 0.33mm))
	(condition "A.isPlated() && B.Type == 'track'"))

(rule "Pad to Track clearance)"
	(constraint clearance (min 0.2mm))
	(condition "A.isPlated() && B.Type == 'track'"))

Thanks for that precious ressource.
I'm pretty noob on kicad still, could you please tell me how to add those custom Design Rules ? On the Board settings I only see "Import Settings from another board"

In Board Setup, Select the Custom Rules tab and cut + paste them in there. There is also a button you can click to check syntax.
This will create a file <board filename>.kicad_dru in your project directory with all your custom rules.

Thanks a lot for the answer.
Pasted, checked for syntax, .kicad_dru generated, all as you said.
But when I check the constraints in the Board Settings afterwards, the specs don't seems to have changed, it's still 0mm for Copper Minimum Track Width for example while your specs say 5mil.
Should I deduce that the Custom Rules supersede the Constraints window settings, and are applied even if it doesn't show there ?

Constraints are global minimums that cant be overriden. Custom rules run after constraints. If a constraint is set to 0, if will just use the settings from net class or custom rules.

For example if you set minimum track width constraint to 5mils and custom rule minimum track width to 10mils, it will use the custom rule value. but you can't set a minimum track width of 4 mils in custom rules.

Also, only a select few custom rules are applied in the pcb editor. Many are only checked when your run your DRC check.

Constraints are global minimums that cant be overriden. Custom rules run after constraints. If a constraint is set to 0, if will just use the settings from net class or custom rules.

For example if you set minimum track width constraint to 5mils and custom rule minimum track width to 10mils, it will use the custom rule value. but you can't set a minimum track width of 4 mils in custom rules.

Also, only a select few custom rules are applied in the pcb editor. Many are only checked when your run your DRC check.

I see, everything's a lot clearer now.
Thanks a lot, good sir. Your help have been extremely useful.

It's a bit sad we have to resort to such methods.
There should be available pre-configured templates that we could import to set everything up to our manufacturers standards, like this big repo of templates of predefined Design Rules for many different PCB manufacturers, importing the templates would even populate some pre-determined useful Track settings. Alas it's a bit old.
https://github.com/sethhillbrand/kicad_templates

You can create your own template with your preferred settings very easily. You probably shouldnt be designing to manufacturer limits anyway unless you really need it.
https://docs.kicad.org/7.0/en/kicad/kicad.html#creating_templates

The link you provided pre-dates Kicad 6 which changed basically everything. I also think custom rules were only added in Kicad 6.

You can create your own template with your preferred settings very easily. You probably shouldnt be designing to manufacturer limits anyway unless you really need it. https://docs.kicad.org/7.0/en/kicad/kicad.html#creating_templates

The link you provided pre-dates Kicad 6 which changed basically everything. I also think custom rules were only added in Kicad 6.

A very big thank you for all those precious informations and for your time 🙏
Wishing you all the best!

Thanks for the script, very easy to add the rules, you save me several minutes :)

I believe ...

(rule "Trace to Outline"
	(constraint edge_clearance (min 0.2mm))
	(condition "A.Type == 'track'"))

... should be (min 0.3mm) according to PCB Manufacturing & Assembly Capabilities (Board Outlines)

Copper to board edge ≥ 0.3 mm
Copper to milled slot ≥ 0.3 mm

/Morten

Thanks, probably that page has been updated to account for router tolerance, since I originally created this script. I have updated it now.

I have created a KiCad-DesignRules GitHub repository that includes a KiCad 7 project with a .kicad_dru file similar to the one in this Gist, but including a PCB Design that covers pass/fail of each rule. This was the only way I could ensure that there were no false positives or false negatives for any of the rules, and that regression errors are not introduced when changing the rule set.

@hattesen Nice one. That seems like a decent way to test the rules.

The trace/space requirement for 4-6 layer boards is 3.5mil (0.09mm). Currently, outer layers are 5mil min regardless of layer count.

The trace/space requirement for 4-6 layer boards is 3.5mil (0.09mm). Currently, outer layers are 5mil min regardless of layer count.

I'll take a look at automatically adjust according to number of layers. Thanks for creating issue labtroll/KiCad-DesignRules#3

Nice work thank you.
But I have a problem, I have a custom footprint, done before added the JLCPCB rules, and if I do check, after adding the rules, now still there are no errors, but if i am in the PCB Editor, I get a lot of errors I did not have before adding the rules. i.e. text thickness in the new rules is 0.15mm but actually 0.1 mm from the footprint when it was designed with the KiCad default rules.
How can I come out of this?

@muekno It's possible to ignore errors in the DRC checker with a right click, then ignore errorr. I personnaly find this practice "OK" to keep my rules for the rest of the board and it is a sort of exception the rules.
If there is a better solution, i would be interested to know.

text thickness in the new rules is 0.15mm but actually 0.1 mm from the footprint when it was designed with the KiCad default rules.

The JLCPCB rules for text are quite conservative to ensure the silkscreen is legible, you can go slightly smaller and probably still get ok results.

@darkxst I asked JLCPCB customer service about the distance from pad to outline, and it's the same as trace to outline. I added this rule to my custom rules, maybe you want to include it in this file:

(rule "Pad to Outline"
	(constraint edge_clearance (min 0.3mm))
	(condition "A.Type == 'pad'"))

Thanks for the rules, it's a great resource.