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daveshah1/gist:3d039adf1cc4c81179bf16d28b134fd9 Secret

Created October 13, 2020 11:40
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Alveo U250 DDR4 init
Raw
gistfile1.txt
litex> sdram_force_cmd_delay 0
Switching SDRAM to software control.
Forcing Cmd delay to 0 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 0 taps.
Data scan:
m0: |1111111111111000000000| delay: -
m1: |1111111111110000000000| delay: -
m2: |1111111110000000000000| delay: -
m3: |1111100000000000000000| delay: -
m4: |0000000000011111111111| delay: 168
m5: |0000000000000000001111| delay: 276
m6: |1000000000000000000011| delay: 308
m7: |1000000000000000000111| delay: 304
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:0 m5:0 m6:0 m7:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |11111111110000000000000000000000| delays: 73+-73
m0, b4: |00000000000111111111111111110000| delays: 306+-126
m0, b5: |00000000000000000000000000000011| delays: 487+-25
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b04 delays: 306+-128
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11111111111111000000000000000000| delays: 106+-106
m1, b4: |00000000000000001111111111111111| delays: 383+-123
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 385+-122
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |01111111111111111000000000000000| delays: 135+-123
m2, b4: |00000000000000000001111111111111| delays: 407+-104
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b03 delays: 132+-126
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |10000000000000000000000000000000| delays: 08+-08
m3, b3: |00001111111111111110000000000000| delays: 169+-120
m3, b4: |00000000000000000000011111111111| delays: 423+-89
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b03 delays: 168+-121
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |01111111111111111000000000000000| delays: 136+-123
m4, b4: |00000000000000000001111111111111| delays: 408+-104
m4, b5: |00000000000000000000000000000000| delays: -
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b03 delays: 137+-126
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |11111111111100000000000000000000| delays: 84+-84
m5, b4: |00000000000000111111111111111000| delays: 335+-122
m5, b5: |00000000000000000000000000000000| delays: 510+-08
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 334+-120
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |11111111000000000000000000000000| delays: 56+-56
m6, b4: |00000000001111111111111110000000| delays: 271+-124
m6, b5: |00000000000000000000000000001111| delays: 473+-38
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b04 delays: 267+-126
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |11110000000000000000000000000000| delays: 34+-34
m7, b4: |00000001111111111111111000000000| delays: 232+-127
m7, b5: |00000000000000000000000001111111| delays: 448+-63
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b04 delays: 230+-129
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 50
Switching SDRAM to software control.
Forcing Cmd delay to 50 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 50 taps.
Data scan:
m0: |1111111111111111000000| delay: -
m1: |1111111111111110000000| delay: -
m2: |1111111111110000000000| delay: -
m3: |1111111100000000000000| delay: -
m4: |0000000000000011111111| delay: 216
m5: |1100000000000000000001| delay: -
m6: |1111000000000000000000| delay: -
m7: |1111000000000000000000| delay: -
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:0 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |11111100000000000000000000000000| delays: 50+-50
m0, b4: |00000000011111111111111110000000| delays: 254+-128
m0, b5: |00000000000000000000000000111111| delays: 467+-45
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b04 delays: 256+-123
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11111111111000000000000000000000| delays: 82+-82
m1, b4: |00000000000000111111111111111000| delays: 337+-122
m1, b5: |00000000000000000000000000000000| delays: 503+-08
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 334+-122
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11111111111111000000000000000000| delays: 105+-105
m2, b4: |00000000000000000111111111111111| delays: 378+-122
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 380+-126
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |01111111111111111000000000000000| delays: 125+-125
m3, b4: |00000000000000000011111111111111| delays: 395+-117
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b03 delays: 123+-122
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |11111111111111000000000000000000| delays: 106+-106
m4, b4: |00000000000000000111111111111111| delays: 382+-121
m4, b5: |00000000000000000000000000000000| delays: -
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 382+-125
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |11110011000000000000000000000000| delays: 08+-08
m5, b4: |00000000000100011000110111000000| delays: 177+-11
m5, b5: |00000000000000000000000000000010| delays: 471+-09
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 175+-08
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |11110000000000000000000000000000| delays: 33+-33
m6, b4: |00000001111111111111110000000000| delays: 217+-120
m6, b5: |00000000000000000000000001111111| delays: 450+-62
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b04 delays: 218+-121
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |11000000000000000000000000000000| delays: 09+-09
m7, b4: |00001111111111111111000000000000| delays: 184+-129
m7, b5: |00000000000000000000001111111111| delays: 430+-81
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b04 delays: 183+-125
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 100
Switching SDRAM to software control.
Forcing Cmd delay to 100 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 100 taps.
Data scan:
m0: |0111111111111111111000| delay: 16
m1: |1111111111111111110000| delay: -
m2: |1111111111111110000000| delay: -
m3: |1111111111100000000000| delay: -
m4: |0000000000000000011111| delay: 265
m5: |1111100000000000000000| delay: -
m6: |1111111000000000000000| delay: -
m7: |1111111000000000000000| delay: -
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:0 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |11110000000000000000000000000000| delays: 23+-23
m0, b4: |00000011111111111111110000000000| delays: 203+-128
m0, b5: |00000000000000000000000011111111| delays: 440+-71
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b04 delays: 209+-128
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11111111000000000000000000000000| delays: 57+-57
m1, b4: |00000000001111111111111111000000| delays: 287+-121
m1, b5: |00000000000000000000000000000111| delays: 476+-36
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 285+-121
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11111111111000000000000000000000| delays: 81+-81
m2, b4: |00000000000001111111111111111000| delays: 329+-122
m2, b5: |00000000000000000000000000000001| delays: 500+-12
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 327+-122
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |11111111111110000000000000000000| delays: 99+-99
m3, b4: |00000000000000011111111111111100| delays: 355+-122
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 356+-128
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |11111111111000000000000000000000| delays: 81+-81
m4, b4: |00000000000000111111111111111000| delays: 334+-124
m4, b5: |00000000000000000000000000000000| delays: 500+-12
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 330+-122
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |11111000000000000000000000000000| delays: 38+-38
m5, b4: |00000000111111111111111000000000| delays: 241+-123
m5, b5: |00000000000000000000000000111111| delays: 459+-52
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 241+-124
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |11000000000000000000000000000000| delays: 08+-08
m6, b4: |00001111111111111110000000000000| delays: 173+-121
m6, b5: |00000000000000000000001111111111| delays: 425+-87
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b04 delays: 170+-127
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00111111111111111000000000000000| delays: 135+-126
m7, b5: |00000000000000000001111111111111| delays: 404+-107
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b04 delays: 136+-129
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 150
Switching SDRAM to software control.
Forcing Cmd delay to 150 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 150 taps.
Data scan:
m0: |0000011111111111111111| delay: 66
m1: |0001111111111111111110| delay: 48
m2: |0111111111111111110000| delay: 02
m3: |1111111111111100000000| delay: -
m4: |1100000000000000000011| delay: 314
m5: |1111111100000000000000| delay: -
m6: |1111111111000000000000| delay: -
m7: |1111111111000000000000| delay: -
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:0 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |10000000000000000000000000000000| delays: 08+-08
m0, b4: |00111111111111111110000000000000| delays: 157+-126
m0, b5: |00000000000000000000011111111111| delays: 416+-95
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b04 delays: 159+-129
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11111000000000000000000000000000| delays: 34+-34
m1, b4: |00000001111111111111111000000000| delays: 233+-125
m1, b5: |00000000000000000000000000111111| delays: 452+-60
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 235+-119
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11111111000000000000000000000000| delays: 56+-56
m2, b4: |00000000001111111111111111000000| delays: 278+-121
m2, b5: |00000000000000000000000000001111| delays: 472+-40
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 278+-120
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |11111111110000000000000000000000| delays: 74+-74
m3, b4: |00000000000011111111111111110000| delays: 305+-123
m3, b5: |00000000000000000000000000000001| delays: 491+-20
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 309+-123
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |11111111000000000000000000000000| delays: 59+-59
m4, b4: |00000000001111111111111111000000| delays: 276+-126
m4, b5: |00000000000000000000000000001111| delays: 474+-37
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 284+-125
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |11000000000000000000000000000000| delays: 12+-12
m5, b4: |00000111111111111111000000000000| delays: 186+-120
m5, b5: |00000000000000000000000111111111| delays: 433+-79
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 191+-124
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |11111111111111110000000000000000| delays: 124+-124
m6, b5: |00000000000000000011111111111111| delays: 407+-105
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b04 delays: 126+-125
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |11111111111111000000000000000000| delays: 104+-104
m7, b5: |00000000000000011111111111111110| delays: 365+-127
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b05 delays: 364+-129
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 200
Switching SDRAM to software control.
Forcing Cmd delay to 200 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 200 taps.
Data scan:
m0: |0000000011111111111111| delay: 116
m1: |0000000111111111111111| delay: 99
m2: |0000111111111111111110| delay: 50
m3: |1111111111111111100000| delay: -
m4: |1111100000000000000000| delay: -
m5: |1111111111110000000000| delay: -
m6: |1111111111111000000000| delay: -
m7: |1111111111111000000000| delay: -
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |11111111111111100000000000000000| delays: 121+-121
m0, b5: |00000000000000000011111111111111| delays: 391+-120
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b04 delays: 120+-120
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |11000000000000000000000000000000| delays: 08+-08
m1, b4: |00001111111111111111000000000000| delays: 186+-119
m1, b5: |00000000000000000000000111111111| delays: 427+-85
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 189+-121
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11110000000000000000000000000000| delays: 34+-34
m2, b4: |00000001111111111111111000000000| delays: 229+-123
m2, b5: |00000000000000000000000011111111| delays: 450+-61
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 229+-129
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |11111110000000000000000000000000| delays: 50+-50
m3, b4: |00000000011111111111111100000000| delays: 262+-127
m3, b5: |00000000000000000000000000001111| delays: 469+-42
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 259+-123
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |11111000000000000000000000000000| delays: 34+-34
m4, b4: |00000001111111111111111000000000| delays: 227+-126
m4, b5: |00000000000000000000000001111111| delays: 453+-58
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 238+-124
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00111111111111111000000000000000| delays: 143+-124
m5, b5: |00000000000000000000111111111111| delays: 410+-102
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b04 delays: 144+-123
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |11111111111110000000000000000000| delays: 100+-100
m6, b5: |00000000000000011111111111111110| delays: 366+-124
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 366+-123
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |11111111111000000000000000000000| delays: 79+-79
m7, b5: |00000000000001111111111111110000| delays: 316+-127
m7, b6: |00000000000000000000000000000001| delays: 499+-12
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b05 delays: 318+-128
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 250
Switching SDRAM to software control.
Forcing Cmd delay to 250 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 250 taps.
Data scan:
m0: |0000000000011111111111| delay: 164
m1: |0000000000111111111111| delay: 149
m2: |0000000111111111111111| delay: 101
m3: |0011111111111111111100| delay: 31
m4: |1111111100000000000000| delay: -
m5: |1111111111111110000000| delay: -
m6: |1111111111111111000000| delay: -
m7: |1111111111111111000000| delay: -
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |11111111111100000000000000000000| delays: 93+-93
m0, b5: |00000000000000111111111111111110| delays: 348+-128
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b05 delays: 349+-129
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |01111111111111111000000000000000| delays: 137+-123
m1, b5: |00000000000000000000111111111111| delays: 405+-107
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b04 delays: 141+-125
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |11000000000000000000000000000000| delays: 08+-08
m2, b4: |00001111111111111111000000000000| delays: 182+-122
m2, b5: |00000000000000000000011111111111| delays: 425+-86
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 185+-126
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |11110000000000000000000000000000| delays: 26+-26
m3, b4: |00000011111111111111110000000000| delays: 208+-125
m3, b5: |00000000000000000000000001111111| delays: 444+-67
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 208+-123
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |11000000000000000000000000000000| delays: 11+-11
m4, b4: |00001111111111111111000000000000| delays: 185+-120
m4, b5: |00000000000000000000001111111111| delays: 428+-84
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 184+-119
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |11111111111111000000000000000000| delays: 108+-108
m5, b5: |00000000000000000111111111111111| delays: 375+-123
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b05 delays: 381+-126
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |11111111110000000000000000000000| delays: 74+-74
m6, b5: |00000000000001111111111111111000| delays: 319+-119
m6, b6: |00000000000000000000000000000001| delays: 492+-19
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 315+-124
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |11111110000000000000000000000000| delays: 56+-56
m7, b5: |00000000011111111111111110000000| delays: 273+-127
m7, b6: |00000000000000000000000000001111| delays: 473+-38
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b05 delays: 274+-124
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 300
Switching SDRAM to software control.
Forcing Cmd delay to 300 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 300 taps.
Data scan:
m0: |0000000000000011111111| delay: 215
m1: |0000000000000111111111| delay: 197
m2: |0000000000111111111111| delay: 149
m3: |0000001111111111111111| delay: 81
m4: |1111111111100000000000| delay: -
m5: |1111111111111111110000| delay: -
m6: |0011111111111111111000| delay: 21
m7: |0111111111111111111000| delay: 16
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |11111111100000000000000000000000| delays: 73+-73
m0, b5: |00000000000011111111111111110000| delays: 297+-130
m0, b6: |00000000000000000000000000000111| delays: 489+-23
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b05 delays: 304+-125
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |11111111111111000000000000000000| delays: 110+-110
m1, b5: |00000000000000000111111111111110| delays: 369+-122
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b05 delays: 368+-124
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |01111111111111110000000000000000| delays: 131+-126
m2, b5: |00000000000000000001111111111111| delays: 400+-111
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b04 delays: 128+-123
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |10000000000000000000000000000000| delays: 10+-08
m3, b4: |00011111111111111100000000000000| delays: 160+-126
m3, b5: |00000000000000000000001111111111| delays: 420+-91
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 163+-126
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |01111111111111110000000000000000| delays: 137+-123
m4, b5: |00000000000000000001111111111111| delays: 401+-111
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b04 delays: 131+-123
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |11111111111000000000000000000000| delays: 82+-82
m5, b5: |00000000000000111111111111110000| delays: 330+-122
m5, b6: |00000000000000000000000000000001| delays: 510+-08
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b05 delays: 332+-124
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |11111110000000000000000000000000| delays: 53+-53
m6, b5: |00000000011111111111111111000000| delays: 270+-122
m6, b6: |00000000000000000000000000011111| delays: 465+-46
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 265+-122
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |11110000000000000000000000000000| delays: 34+-34
m7, b5: |00000001111111111111110000000000| delays: 223+-129
m7, b6: |00000000000000000000000011111111| delays: 450+-62
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b05 delays: 222+-127
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 350
Switching SDRAM to software control.
Forcing Cmd delay to 350 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 350 taps.
Data scan:
m0: |0000000000000000011111| delay: 264
m1: |0000000000000000111111| delay: 248
m2: |0000000000000111111111| delay: 199
m3: |0000000001111111111111| delay: 130
m4: |1111111111111100000000| delay: -
m5: |0001111111111111111110| delay: 42
m6: |0000011111111111111111| delay: 71
m7: |0000011111111111111111| delay: 65
Write latency calibration:
m0:6 m1:6 m2:0 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |11111100000000000000000000000000| delays: 43+-43
m0, b5: |00000000011111111111111100000000| delays: 253+-127
m0, b6: |00000000000000000000000000111111| delays: 463+-48
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b05 delays: 249+-129
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |11111111111000000000000000000000| delays: 81+-81
m1, b5: |00000000000001111111111111110000| delays: 319+-122
m1, b6: |00000000000000000000000000000000| delays: 507+-08
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b05 delays: 327+-122
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b00 delays: -
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |11111111111111110000000000000000| delays: 119+-119
m3, b5: |00000000000000000011111111111111| delays: 392+-120
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b04 delays: 121+-121
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |11111111111110000000000000000000| delays: 102+-102
m4, b5: |00000000000000001111111111111110| delays: 367+-124
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b05 delays: 364+-126
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |11111111000000000000000000000000| delays: 56+-56
m5, b5: |00000000000111111111111111000000| delays: 277+-123
m5, b6: |00000000000000000000000000000111| delays: 484+-27
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b05 delays: 277+-122
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |11110000000000000000000000000000| delays: 28+-28
m6, b5: |00000001111111111111110000000000| delays: 218+-119
m6, b6: |00000000000000000000000011111111| delays: 442+-69
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 220+-118
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |11000000000000000000000000000000| delays: 08+-08
m7, b5: |00011111111111111110000000000000| delays: 171+-131
m7, b6: |00000000000000000000011111111111| delays: 424+-88
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b05 delays: 174+-132
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 400
Switching SDRAM to software control.
Forcing Cmd delay to 400 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 400 taps.
Data scan:
m0: |1000000000000000000011| delay: 312
m1: |0000000000000000000111| delay: 297
m2: |0000000000000000111111| delay: 245
m3: |0000000000001111111111| delay: 179
m4: |1111111111111111100000| delay: -
m5: |0000001111111111111111| delay: 90
m6: |0000000011111111111111| delay: 121
m7: |0000000011111111111111| delay: 115
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |11100000000000000000000000000000| delays: 20+-20
m0, b5: |00000011111111111111100000000000| delays: 204+-129
m0, b6: |00000000000000000000000111111111| delays: 441+-70
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b05 delays: 202+-130
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |11111111000000000000000000000000| delays: 55+-55
m1, b5: |00000000001111111111111111000000| delays: 270+-125
m1, b6: |00000000000000000000000000000111| delays: 482+-29
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b05 delays: 269+-124
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |10110010010000000000000000000000| delays: 08+-08
m2, b5: |00000000000010111111101001100000| delays: 199+-09
m2, b6: |00000000000000000000000000000000| delays: 493+-11
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b05 delays: 200+-09
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |11111111111100000000000000000000| delays: 94+-94
m3, b5: |00000000000000011111111111111100| delays: 351+-128
m3, b6: |00000000000000000000000000000000| delays: 514+-08
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b05 delays: 348+-120
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |11111111111000000000000000000000| delays: 80+-80
m4, b5: |00000000000001111111111111110000| delays: 315+-121
m4, b6: |00000000000000000000000000000001| delays: 503+-08
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b05 delays: 316+-121
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |11111000000000000000000000000000| delays: 32+-32
m5, b5: |00000000111111111111111000000000| delays: 229+-123
m5, b6: |00000000000000000000000000111111| delays: 459+-53
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b05 delays: 236+-123
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |10000000000000000000000000000000| delays: 08+-08
m6, b5: |00001111111111111100000000000000| delays: 167+-124
m6, b6: |00000000000000000000011111111111| delays: 416+-96
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 176+-124
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00000000000000000000000000000000| delays: -
m7, b5: |00000000000000000000000000000000| delays: 20+-08
m7, b6: |00000000000000000000000000000000| delays: 308+-08
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b05 delays: 46+-08
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 450
Switching SDRAM to software control.
Forcing Cmd delay to 450 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 450 taps.
Data scan:
m0: |1111000000000000000000| delay: -
m1: |1110000000000000000000| delay: -
m2: |0000000000000000000111| delay: 295
m3: |0000000000000001111111| delay: 228
m4: |0001111111111111111100| delay: 33
m5: |0000000001111111111111| delay: 141
m6: |0000000000011111111111| delay: 172
m7: |0000000000011111111111| delay: 165
Write latency calibration:
m0:0 m1:0 m2:0 m3:6 m4:6 m5:6 m6:6 m7:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b00 delays: -
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b00 delays: -
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b00 delays: -
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |11111111110000000000000000000000| delays: 71+-71
m3, b5: |00000000000011111111111111110000| delays: 305+-127
m3, b6: |00000000000000000000000000000011| delays: 489+-22
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b05 delays: 299+-122
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |11111111000000000000000000000000| delays: 61+-61
m4, b5: |00000000011111111111111110000000| delays: 273+-126
m4, b6: |00000000000000000000000000001111| delays: 478+-34
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b05 delays: 268+-123
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |11000000000000000000000000000000| delays: 09+-09
m5, b5: |00001111111111111111000000000000| delays: 185+-119
m5, b6: |00000000000000000000001111111111| delays: 434+-78
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b05 delays: 183+-124
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00000000000000000000000000000000| delays: -
m6, b5: |11111111111111110000000000000000| delays: 122+-121
m6, b6: |00000000000000000011111111111111| delays: 393+-119
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b05 delays: 123+-122
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00000000000000000000000000000000| delays: -
m7, b5: |00000000000000000000000000000000| delays: -
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b00 delays: -
Switching SDRAM to hardware control.
litex> sdram_force_cmd_delay 500
Switching SDRAM to software control.
Forcing Cmd delay to 500 taps
Switching SDRAM to hardware control.
litex> sdram_cal
Switching SDRAM to software control.
Write leveling:
Setting Cmd/Clk delay to 500 taps.
Data scan:
m0: |1111111100000000000000| delay: -
m1: |1111110000000000000000| delay: -
m2: |1110000000000000000000| delay: -
m3: |0000000000000000001111| delay: 275
m4: |0000001111111111111111| delay: 84
m5: |0000000000001111111111| delay: 189
m6: |0000000000000011111111| delay: 221
m7: |0000000000000011111111| delay: 213
Write latency calibration:
m0:0 m1:0 m2:0 m3:6 m4:6 m5:0 m6:0 m7:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b00 delays: -
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b00 delays: -
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b00 delays: -
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |11111100000000000000000000000000| delays: 51+-51
m3, b5: |00000000011111111111111100000000| delays: 258+-124
m3, b6: |00000000000000000000000000011111| delays: 463+-49
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b05 delays: 252+-118
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |11110000000000000000000000000000| delays: 33+-33
m4, b5: |00000001111111111111110000000000| delays: 217+-121
m4, b6: |00000000000000000000000011111111| delays: 453+-58
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b05 delays: 219+-124
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00000000000000000000000000000000| delays: -
m5, b5: |00000000000000000000000000000000| delays: -
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b00 delays: -
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00000000000000000000000000000000| delays: -
m6, b5: |00000000000000000000000000000000| delays: -
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b00 delays: -
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00000000000000000000000000000000| delays: -
m7, b5: |00000000000000000000000000000000| delays: -
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b00 delays: -
Switching SDRAM to hardware control.
litex>
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