comparador1bit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparadorvhdl is
    Port ( eq : out  STD_LOGIC;
           A : in  STD_LOGIC;
           B : in  STD_LOGIC);
end comparadorvhdl;

architecture sop_arch of comparadorvhdl is

signal p0, p1: std_logic;

begin

	eq<=p0 or p1;

	p0<=(not A) and (not B);

	p1<=A and B;
	
end sop_arch;