encoderp_sym

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY encoderp_sym IS
END encoderp_sym;
 
ARCHITECTURE tb_arch OF encoderp_sym IS 
 
	signal test_r: std_logic_vector(4 downto 1);
	signal test_pcode: std_logic_vector(2 downto 0);
 
begin
	uut: entity work.Priority_encoder(cond_arch)
	port map(r => test_r, pcode=> test_pcode);
	process
		begin
		test_r<="1000";
		wait for 100 ns;
		test_r<="0100";
		wait for 100 ns;
		test_r<="0010";
		wait for 100 ns;
		test_r<="0001";
		wait for 100 ns;
		test_r<="0000";
		wait for 100 ns;
		
		test_r<="1111";
		wait for 100 ns;
		test_r<="0111";
		wait for 100 ns;
		test_r<="0011";
		wait for 100 ns;
		test_r<="0001";
		wait for 100 ns;
		test_r<="0000";
		wait for 100 ns;
	end process;
 
end tb_arch;