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void write_eeprom(uint16_t addr, uint8_t data)
{
  // first read the data on the current address, if it's the same we can save some time
  HAL_GPIO_WritePin(CPU_CTRL_PORT, CPU_MREQ_PIN, LOW);
  HAL_GPIO_WritePin(CPU_CTRL_PORT, CPU_RD_PIN, LOW);
  HAL_GPIO_WritePin(CPU_CTRL_PORT, CPU_WR_PIN, HIGH);
  uint8_t exsiting_byte = CPU_DATA_PORT->IDR & 0xff;

  if(exsiting_byte == data)
    return;

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void program_mode()
{
  // pull down BUSREQ
  HAL_GPIO_WritePin(CPU_CTRL_PORT, CPU_BUSREQ_PIN, LOW);\
  // cycle clock until BUSACK is low, now CPU is kicked off the bus
  while(HAL_GPIO_ReadPin(CPU_CTRL_PORT, CPU_BUSACK_PIN) != LOW)
    cycle_clock(1);

  // switch memory control signals to output to take over the bus
  GPIO_InitTypeDef GPIO_InitStruct;

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	org	0x0
start	jmp	start

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	org	0x0		; program starts at address 0x0
	xor	A		; clear A
	ld	sp, 0x7fff	; set up stack
start	add	0x10		; add 0x10 to A
	push	AF		; push AF to stack
	jmp	start

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import sys
import time
import serial

ser = serial.Serial(sys.argv[1], 115200, timeout=0.5) 
print("connected")

def read_eep(addr):
	while 1:
		print("reading addr " + str(addr) + "...")

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// display 100% saturation colorbars
// ------------------------
// Combinational "always block", which is a block that is
// triggered when anything in the "sensitivity list" changes.
// The asterisk implies that everything that is capable of triggering the block
// is automatically included in the sensitivty list.  In this case, it would be
// equivalent to the following: always @(hc, vc)
// Assignment statements can only be used on type "reg" and should be of the "blocking" type: =
always @(*)
begin

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always @(*)
begin
	// inside active region
	if ((vc >= vbp && vc < vfp) && (hc >= hbp && hc < hfp))
	begin
		vram_rd_low = 0;
		hpos = hc - hbp;
		vpos = vc - vbp;
		hdot = hpos[2:0];
		vdot = vpos[3:0];

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always @(posedge clk50)
begin
	// inside active region
	if ((vc >= vbp && vc < vfp) && (hc >= hbp && hc < hfp))
	begin
		front_vram_rd_low = 0;
		hpos = hc - hbp;
		vpos = vc - vbp;
		hdot = hpos[2:0];
		vdot = vpos[3:0];

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module buffer_copier(
	input wire clk,
	input wire vblank,
	output reg front_vram_wr_low,
	output reg back_vram_rd_low,
	output reg copy_in_progress,
	inout wire [7:0] front_vram_data,
	inout wire [7:0] back_vram_data,
	output wire [12:0] front_vram_addr,

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module cpu_vreg(
	input wire clk,
	input wire copy_in_progress,
	input wire cpu_rd,
	input wire cpu_wr,
	input wire cpu_mreq,
	input wire [15:0] cpu_addr,
	inout wire [7:0] cpu_data,
	output reg back_vram_wr_low,