Skip to content

Instantly share code, notes, and snippets.

@devarsht

devarsht/v6_v5_rangediff_am62l.txt

Created May 7, 2025 12:50
Show Gist options
  • Save devarsht/f64b00754794d22e57ac18ec09a7b019 to your computer and use it in GitHub Desktop.
Save devarsht/f64b00754794d22e57ac18ec09a7b019 to your computer and use it in GitHub Desktop.
Download ZIP
v6_v5_rangediff_am62l
Raw
v6_v5_rangediff_am62l.txt
1: f36a4c3b069f = 1: e7e7e99be4dc dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
2: 7d6ce8735b92 ! 2: 5bdec3be79d8 drm/tidss: Update infrastructure to support K3 DSS cut-down versions
@@ drivers/gpu/drm/tidss/tidss_crtc.c: static void tidss_crtc_atomic_disable(struct
* the layers here as a work-around.
*/
- for (u32 layer = 0; layer < tidss->feat->num_planes; layer++)
-- dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer,
-- false);
-+ for (u32 layer = 0; layer < tidss->feat->num_vids; layer++) {
-+ u32 hw_id = tidss->feat->vid_info[layer].hw_id;
-+
-+ dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport,
-+ hw_id, false);
-+ }
-
- dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport);
++ for (u32 layer = 0; layer < tidss->feat->num_vids; layer++)
+ dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer,
+ false);
## drivers/gpu/drm/tidss/tidss_dispc.c ##
@@ drivers/gpu/drm/tidss/tidss_dispc.c: const struct dispc_features dispc_am62a7_fe
};
static const u16 *dispc_common_regmap;
+@@ drivers/gpu/drm/tidss/tidss_dispc.c: static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
+ static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
+ u32 hw_plane)
+ {
+- u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));
++ u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
++ u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_id));
+
+ return dispc_vid_irq_from_raw(stat, hw_plane);
+ }
+@@ drivers/gpu/drm/tidss/tidss_dispc.c: static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
+ static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
+ u32 hw_plane, dispc_irq_t vidstat)
+ {
++ u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
+ u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
+
+- dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);
++ dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_id), stat);
+ }
+
+ static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
+@@ drivers/gpu/drm/tidss/tidss_dispc.c: static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
+ static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
+ u32 hw_plane)
+ {
+- u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));
++ u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
++ u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_id));
+
+ return dispc_vid_irq_from_raw(stat, hw_plane);
+ }
+@@ drivers/gpu/drm/tidss/tidss_dispc.c: static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
+ static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
+ u32 hw_plane, dispc_irq_t vidstat)
+ {
++ u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
+ u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
+
+- dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);
++ dispc_write(dispc, DISPC_VID_IRQENABLE(hw_id), stat);
+ }
+
+ static
@@ drivers/gpu/drm/tidss/tidss_dispc.c: void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
if (clearmask & DSS_IRQ_VP_MASK(i))
dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
@@ drivers/gpu/drm/tidss/tidss_dispc.c: void dispc_k3_clear_irqstatus(struct dispc_
- for (i = 0; i < dispc->feat->num_planes; ++i) {
+
+ for (i = 0; i < dispc->feat->num_vids; ++i) {
-+ u32 hw_id = dispc->feat->vid_info[i].hw_id;
-+
if (clearmask & DSS_IRQ_PLANE_MASK(i))
-- dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
-+ dispc_k3_vid_write_irqstatus(dispc, hw_id, clearmask);
+ dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
}
-
- /* always clear the top level irqstatus */
@@ drivers/gpu/drm/tidss/tidss_dispc.c: dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
for (i = 0; i < dispc->feat->num_vps; ++i)
status |= dispc_k3_vp_read_irqstatus(dispc, i);
- for (i = 0; i < dispc->feat->num_planes; ++i)
-- status |= dispc_k3_vid_read_irqstatus(dispc, i);
+ for (i = 0; i < dispc->feat->num_vids; ++i) {
-+ u32 hw_id = dispc->feat->vid_info[i].hw_id;
-+
-+ status |= dispc_k3_vid_read_irqstatus(dispc, hw_id);
+ status |= dispc_k3_vid_read_irqstatus(dispc, i);
+ }
dispc_k3_clear_irqstatus(dispc, status);
@@ drivers/gpu/drm/tidss/tidss_dispc.c: static dispc_irq_t dispc_k3_read_irqenable(
enable |= dispc_k3_vp_read_irqenable(dispc, i);
- for (i = 0; i < dispc->feat->num_planes; ++i)
-- enable |= dispc_k3_vid_read_irqenable(dispc, i);
+ for (i = 0; i < dispc->feat->num_vids; ++i) {
-+ u32 hw_id = dispc->feat->vid_info[i].hw_id;
-+
-+ enable |= dispc_k3_vid_read_irqenable(dispc, hw_id);
+ enable |= dispc_k3_vid_read_irqenable(dispc, i);
+ }
return enable;
@@ drivers/gpu/drm/tidss/tidss_dispc.c: static void dispc_k3_set_irqenable(struct d
}
- for (i = 0; i < dispc->feat->num_planes; ++i) {
-- dispc_k3_vid_set_irqenable(dispc, i, mask);
+ for (i = 0; i < dispc->feat->num_vids; ++i) {
+ u32 hw_id = dispc->feat->vid_info[i].hw_id;
+
-+ dispc_k3_vid_set_irqenable(dispc, hw_id, mask);
+ dispc_k3_vid_set_irqenable(dispc, i, mask);
+
if (mask & DSS_IRQ_PLANE_MASK(i))
- main_enable |= BIT(i + 4); /* VID IRQ */
@@ drivers/gpu/drm/tidss/tidss_dispc.c: static void dispc_k3_set_irqenable(struct d
if (main_disable)
dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
+@@ drivers/gpu/drm/tidss/tidss_dispc.c: static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
+ u32 hw_plane, u32 hw_videoport,
+ u32 x, u32 y, u32 layer)
+ {
++ u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
++
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
+- hw_plane, 4, 1);
++ hw_id, 4, 1);
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
+ x, 17, 6);
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
+@@ drivers/gpu/drm/tidss/tidss_dispc.c: static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
+ u32 hw_plane, u32 hw_videoport,
+ u32 x, u32 y, u32 layer)
+ {
++ u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
++
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
+- hw_plane, 4, 1);
++ hw_id, 4, 1);
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
+ x, 13, 0);
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
@@ drivers/gpu/drm/tidss/tidss_dispc.c: int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
const struct drm_plane_state *state,
u32 hw_videoport)
3: fb2c6d0ac2f1 = 3: d43f105c2dc3 drm/tidss: Add support for AM62L display subsystem
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment