BundleとRegInitで作る初期化済みレジスタ（コンパニオン・オブジェクト版）から生成したRTL

SampleBundleRegInit2.v

module SampleBundleRegInit2(
  input         clock,
  input         reset,
  input         io_en,
  input  [31:0] io_data,
  output [3:0]  io_out1_a,
  output [3:0]  io_out1_b,
  output [3:0]  io_out2_a,
  output [3:0]  io_out2_b
);
  reg [3:0] out1_a; // @[BundleRegInit2.scala 69:21]
  reg [31:0] _RAND_0;
  reg [3:0] out1_b; // @[BundleRegInit2.scala 69:21]
  reg [31:0] _RAND_1;
  reg [3:0] out2_a; // @[BundleRegInit2.scala 70:21]
  reg [31:0] _RAND_2;
  reg [3:0] out2_b; // @[BundleRegInit2.scala 70:21]
  reg [31:0] _RAND_3;
  wire [3:0] _T_24; // @[BundleRegInit2.scala 27:14]
  wire [3:0] _T_25; // @[BundleRegInit2.scala 28:14]
  wire [3:0] _GEN_0; // @[BundleRegInit2.scala 72:16]
  wire [3:0] _GEN_1; // @[BundleRegInit2.scala 72:16]
  wire [3:0] _GEN_2; // @[BundleRegInit2.scala 72:16]
  wire [3:0] _GEN_3; // @[BundleRegInit2.scala 72:16]
  assign _T_24 = io_data[3:0]; // @[BundleRegInit2.scala 27:14]
  assign _T_25 = io_data[7:4]; // @[BundleRegInit2.scala 28:14]
  assign _GEN_0 = io_en ? _T_24 : out1_a; // @[BundleRegInit2.scala 72:16]
  assign _GEN_1 = io_en ? _T_25 : out1_b; // @[BundleRegInit2.scala 72:16]
  assign _GEN_2 = io_en ? _T_24 : out2_a; // @[BundleRegInit2.scala 72:16]
  assign _GEN_3 = io_en ? _T_25 : out2_b; // @[BundleRegInit2.scala 72:16]
  assign io_out1_a = out1_a; // @[BundleRegInit2.scala 77:11]
  assign io_out1_b = out1_b; // @[BundleRegInit2.scala 77:11]
  assign io_out2_a = out2_a; // @[BundleRegInit2.scala 78:11]
  assign io_out2_b = out2_b; // @[BundleRegInit2.scala 78:11]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      #0.002 begin end
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  out1_a = _RAND_0[3:0];
  `endif // RANDOMIZE_REG_INIT
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  out1_b = _RAND_1[3:0];
  `endif // RANDOMIZE_REG_INIT
  `ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  out2_a = _RAND_2[3:0];
  `endif // RANDOMIZE_REG_INIT
  `ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  out2_b = _RAND_3[3:0];
  `endif // RANDOMIZE_REG_INIT
  end
`endif // RANDOMIZE
  always @(posedge clock) begin
    if (reset) begin
      out1_a <= 4'h3;
    end else begin
      if (io_en) begin
        out1_a <= _T_24;
      end
    end
    if (reset) begin
      out1_b <= 4'h4;
    end else begin
      if (io_en) begin
        out1_b <= _T_25;
      end
    end
    if (reset) begin
      out2_a <= 4'h7;
    end else begin
      if (io_en) begin
        out2_a <= _T_24;
      end
    end
    if (reset) begin
      out2_b <= 4'h7;
    end else begin
      if (io_en) begin
        out2_b <= _T_25;
      end
    end
  end
endmodule