What doesn't get measured might not get done.
- Covergroup should be wrapped in a class:
class my_cg_mon extends uvm_subscriber #(my_txn);
covergroup my_cg;
option.per_instance = 1;
endgroup : my_cg
function new(string name = "my_cg_mon", uvm_component parent = null);
my_cg = new();
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
my_cg.set_inst_name("my_cg_name"); // get_full_name() for UVM hierarchy path
endfunction : build_phase
// call my_cg.sample() to capture coverage
endclass : my_cg_mon
- UART Line Control Register (LCR) example:
bit [5:0] lcr;
covergroup lcr_cg;
data : coverpoint lcr[1:0] {
bins bits_5 = {0};
bins bits_6 = {1};
bins bits_7 = {2};
bins bits_8 = {3};
}
stop : coverpoint lcr[2] {
bins stop_0 = {0};
bins stop_1 = {1};
}
parity : coverpoint lcr[5:3] {
bins none = {3'b000, 3'b010, 3'b100, 3'b110}; // single bin, multiple values
bins odd = {3'b001};
bins even = {3'b011};
bins stick_0 = {3'b101};
bins stick_1 = {3'b111};
}
word_format : cross bits, stop, parity;
endgroup : lcr_cg
- Ignore bins
bit [2:0] bits;
coverpoint bits {
bins bits_0 = {0};
// [..]
ignore_bins = {3'b100}; // or, illegal_bins
}
- Array of bins
bit [2:0] bits;
coverpoint bits {
bins multi_bins[] = {3'b000, 3'b001, 3'b010, 3'b011}; // 3 bins created
}
- User defined cross coverage bins
This excludes writes for addr0.
ADDRESS : coverpoint addr {
bins addr0 = {0};
bins addr1 = {1};
}
CMD : coverpoint cmd {
bins READ = {0};
bins WRITE = {1};
bins IDLE = {2};
}
X_ADDRESS_CMD : cross ADDRESS, CMD {
ignore_bins AUTO_ADDR_WRITE = binsof(CMD) intersect {1} && binsof(ADDRESS) intersect {0};
}