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View uvm.md

UVM Basics

UVM employs a layered, object-oriented approach to testbench development.

uvm_sequence_item is a uvm_object that contains data fields to implement protocols and communicate with with DUT. uvm_driver is responsible for converted the sequence item(s) into "pin wiggles". The sequence_item(s) are provided by one uvm_sequence objects that define stimulus at the transaction level and execute on the agent's uvm_sequencer component. The sequencer is responsible for executing the sequences, arbitrating between them, and routing sequence items between the driver and the sequence.

UVM agents have a configuration object that allows the test writer to control how the testbench is assembled and executed.

Components

View coverage_cookbook.md

Theory

What doesn't get measured might not get done.

  • Covergroup should be wrapped in a class:
class my_cg_mon extends uvm_subscriber #(my_txn);

  covergroup my_cg;
View virtualbox.md

Notes

  • Start Ubuntu at command line

Edit /etc/defaults/grub.

#GRUB_CMDLINE_LINUX_DEFAULT="splash quiet"
GRUB_CMDLINE_LINUX="3"

sudo update-grub
View rock.md

I used to work on Rock. Getting around to re-read some papers on it.

SST: A Novel Architecture Implemented in Sun's ROCK Processor

SST hardware dynamically extracts two threads of execution from a single sequential program. SST uses an "efficient" checkpointing mechanism to eliminate the need for renaming logic, reorder buffer, memory disambiguation, issue windows, etc.

SST uses a traditional multithreaded pipeline with an additional mechanism to checkpoint the register file.

SST implements two hardware thread (ahead and behind). Ahead thread speculatively executes under a cache miss and speculatively retires instructions out of order. A behind thread executes instructions dependent on the cache miss.

View scala_for_ml.md

Notes for 'Scala for Machine Learning, P. Nicolas" url

  • Chapter 1

Critical to understand the different classes of ML algorithms and to select the ones that are relevant to the domain.

ML problems are categorized as classification, prediction, optimization, and regression.

  • Classification is to extract knowledge for historical data. For example, a classifier can be built to identify a disease from a set of symptoms.
View neuromem.md

CM1K Chip

Each neuron consists of SRAM and a small programmable logic unit. The logic is prewired to run certrain types of algorithms. Neurons are interconnected using a small bidir bus.

Released in 2007. Follow up to IBM ZISC chip. ZISC refers to an architecture based solely on pattern matching and the abscense of micro-instructions. A single ZISC036 holds 36 neurons to implement an RBF network trained with the RCE (or ROI) algorithm.

ZISC employs Radial Basis Function (RBF) and K-Nearest Neighbor (KNN) algorithms. ZISC approach is a specialized but cheap chip to do one thing very quickly.

  • RBF: Real-valued function whose value depends only on the distance from the origin. Used as a kernel in support vector classification. Can be interpreted as a simple single-layer type of ANN.
  • KNN: Stores all avalable cases and classifies new cases based on a similarly measure (e.g. distance function). Used in statistical estimation and pattern recognition.
View ulimit.md
View cmake.md

Why CMake? Why? It is only me or do I find CMake to be convoluted and non intuitive?

  • Debug vs. Release:

Technically, this is all that is needed:

cmake -DCMAKE_BUILD_TYPE=Release ..
cmake -DCMAKE_BUILD_TYPE=Debug ..
View scala.md

Scala Notes

Variables

Immutable and mutable

Scala has two kinds of variables, vals and vars:

  • val is immutable, cannot be reassigned
  • var is mutable, can be reassigned
View riscv_debug_spec.md

Chapter 2

Each hart in the platform is controlled by exactly one DM? But, usually all harts in a single core are controlled by the same DM.

Abstract commands provide access to GPRs. Addt. registers are accessible through abstract commands or by writing to the optional program buffer.

The program buffer allows the debugger to execute arbitrary instructions on a hart. A bus access block allows memory access without using a RISC-V hart to perform the access.

Chapter 3