- Clone repositories
% cd llvmrepos % git clone https://git.llvm.org/git/llvm.git/ % git config branch.master.rebase true
curl -sL https://packagecloud.io/AtomEditor/atom/gpgkey | sudo apt-key add - sudo sh -c 'echo "deb [arch=amd64] https://packagecloud.io/AtomEditor/atom/any/ any main" > /etc/apt/sources.list.d/atom.list' sudo apt-get update
$ sudo apt-get install git $ sudo apt-get install default-jdk # OPTIONAL $ wget https://gerrit-releases.storage.googleapis.com/gerrit-2.15.5.war $ java -jar gerrit-2.15.war init --batch -d ~/gerrit
UVM employs a layered, object-oriented approach to testbench development.
uvm_sequence_item is a
uvm_object that contains data fields to implement protocols and communicate with with DUT.
uvm_driver is responsible for converted the sequence item(s) into "pin wiggles". The sequence_item(s) are provided by one
uvm_sequence objects that define stimulus at the transaction level and execute on the agent's
uvm_sequencer component. The sequencer is responsible for executing the sequences, arbitrating between them, and routing sequence items between the driver and the sequence.
UVM agents have a configuration object that allows the test writer to control how the testbench is assembled and executed.
I used to work on Rock. Getting around to re-read some papers on it.
SST hardware dynamically extracts two threads of execution from a single sequential program. SST uses an "efficient" checkpointing mechanism to eliminate the need for renaming logic, reorder buffer, memory disambiguation, issue windows, etc.
SST uses a traditional multithreaded pipeline with an additional mechanism to checkpoint the register file.
SST implements two hardware thread (ahead and behind). Ahead thread speculatively executes under a cache miss and speculatively retires instructions out of order. A behind thread executes instructions dependent on the cache miss.
Critical to understand the different classes of ML algorithms and to select the ones that are relevant to the domain.
ML problems are categorized as classification, prediction, optimization, and regression.
Each neuron consists of SRAM and a small programmable logic unit. The logic is prewired to run certrain types of algorithms. Neurons are interconnected using a small bidir bus.
Released in 2007. Follow up to IBM ZISC chip. ZISC refers to an architecture based solely on pattern matching and the abscense of micro-instructions. A single ZISC036 holds 36 neurons to implement an RBF network trained with the RCE (or ROI) algorithm.
ZISC employs Radial Basis Function (RBF) and K-Nearest Neighbor (KNN) algorithms. ZISC approach is a specialized but cheap chip to do one thing very quickly.
/etc/security/limits.conf. For non-GUI login:
# FIXME: is * and root required? @plus soft nofile 131072 @plus hard nofile 131072