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UVM Basics

UVM employs a layered, object-oriented approach to testbench development.

uvm_sequence_item is a uvm_object that contains data fields to implement protocols and communicate with with DUT. uvm_driver is responsible for converted the sequence item(s) into "pin wiggles". The sequence_item(s) are provided by one uvm_sequence objects that define stimulus at the transaction level and execute on the agent's uvm_sequencer component. The sequencer is responsible for executing the sequences, arbitrating between them, and routing sequence items between the driver and the sequence.

UVM agents have a configuration object that allows the test writer to control how the testbench is assembled and executed.




What doesn't get measured might not get done.

  • Covergroup should be wrapped in a class:
class my_cg_mon extends uvm_subscriber #(my_txn);

  covergroup my_cg;


  • Start Ubuntu at command line

Edit /etc/defaults/grub.


sudo update-grub

I used to work on Rock. Getting around to re-read some papers on it.

SST: A Novel Architecture Implemented in Sun's ROCK Processor

SST hardware dynamically extracts two threads of execution from a single sequential program. SST uses an "efficient" checkpointing mechanism to eliminate the need for renaming logic, reorder buffer, memory disambiguation, issue windows, etc.

SST uses a traditional multithreaded pipeline with an additional mechanism to checkpoint the register file.

SST implements two hardware thread (ahead and behind). Ahead thread speculatively executes under a cache miss and speculatively retires instructions out of order. A behind thread executes instructions dependent on the cache miss.


Notes for 'Scala for Machine Learning, P. Nicolas" url

  • Chapter 1

Critical to understand the different classes of ML algorithms and to select the ones that are relevant to the domain.

ML problems are categorized as classification, prediction, optimization, and regression.

  • Classification is to extract knowledge for historical data. For example, a classifier can be built to identify a disease from a set of symptoms.

CM1K Chip

Each neuron consists of SRAM and a small programmable logic unit. The logic is prewired to run certrain types of algorithms. Neurons are interconnected using a small bidir bus.

Released in 2007. Follow up to IBM ZISC chip. ZISC refers to an architecture based solely on pattern matching and the abscense of micro-instructions. A single ZISC036 holds 36 neurons to implement an RBF network trained with the RCE (or ROI) algorithm.

ZISC employs Radial Basis Function (RBF) and K-Nearest Neighbor (KNN) algorithms. ZISC approach is a specialized but cheap chip to do one thing very quickly.

  • RBF: Real-valued function whose value depends only on the distance from the origin. Used as a kernel in support vector classification. Can be interpreted as a simple single-layer type of ANN.
  • KNN: Stores all avalable cases and classifies new cases based on a similarly measure (e.g. distance function). Used in statistical estimation and pattern recognition.