Link to FIRRTL specification here
All FIRRTL circuits consist of a list of modules. Each module as a name, list of ports, and statements.
Types are used to specify the structure of data. Here are examples:
Link to FIRRTL specification here
All FIRRTL circuits consist of a list of modules. Each module as a name, list of ports, and statements.
Types are used to specify the structure of data. Here are examples:
Link to book: https://www.amazon.com/Hands-Machine-Learning-Scikit-Learn-TensorFlow/dp/1491962291
ML is the field of study that gives computers the ability to learn without being explicitly programmed.
A spam filter based on ML techniques automatically learns which words and phrases are god predictors of spam by blocking unusually frequent pattern of words.
A second example where ML shines is for problems that are either too complex or have no known algorithm; speech recognition, for example.
https://llvm.org/docs/GettingStarted.html
% cd llvmrepos
% git clone https://git.llvm.org/git/llvm.git/
% git config branch.master.rebase true
From https://flight-manual.atom.io/getting-started/sections/installing-atom/:
curl -sL https://packagecloud.io/AtomEditor/atom/gpgkey | sudo apt-key add -
sudo sh -c 'echo "deb [arch=amd64] https://packagecloud.io/AtomEditor/atom/any/ any main" > /etc/apt/sources.list.d/atom.list'
sudo apt-get update
$ sudo apt-get install git
$ sudo apt-get install default-jdk # OPTIONAL
$ wget https://gerrit-releases.storage.googleapis.com/gerrit-2.15.5.war
$ java -jar gerrit-2.15.war init --batch -d ~/gerrit
https://www.digitalocean.com/community/tutorials/how-to-install-gerrit-on-an-ubuntu-cloud-server
UVM employs a layered, object-oriented approach to testbench development.
uvm_sequence_item
is a uvm_object
that contains data fields to implement protocols and communicate with with DUT. uvm_driver
is responsible for converted the sequence item(s) into "pin wiggles". The sequence_item(s) are provided by one uvm_sequence
objects that define stimulus at the transaction level and execute on the agent's uvm_sequencer
component. The sequencer is responsible for executing the sequences, arbitrating between them, and routing sequence items between the driver and the sequence.
UVM agents have a configuration object that allows the test writer to control how the testbench is assembled and executed.
I used to work on Rock. Getting around to re-read some papers on it.
SST hardware dynamically extracts two threads of execution from a single sequential program. SST uses an "efficient" checkpointing mechanism to eliminate the need for renaming logic, reorder buffer, memory disambiguation, issue windows, etc.
SST uses a traditional multithreaded pipeline with an additional mechanism to checkpoint the register file.
SST implements two hardware thread (ahead and behind). Ahead thread speculatively executes under a cache miss and speculatively retires instructions out of order. A behind thread executes instructions dependent on the cache miss.