View scala_for_ml.md

Notes for 'Scala for Machine Learning, P. Nicolas" url

  • Chapter 1

Critical to understand the different classes of ML algorithms and to select the ones that are relevant to the domain.

ML problems are categorized as classification, prediction, optimization, and regression.

  • Classification is to extract knowledge for historical data. For example, a classifier can be built to identify a disease from a set of symptoms.
View neuromem.md

CM1K Chip

Each neuron consists of SRAM and a small programmable logic unit. The logic is prewired to run certrain types of algorithms. Neurons are interconnected using a small bidir bus.

Released in 2007. Follow up to IBM ZISC chip. ZISC refers to an architecture based solely on pattern matching and the abscense of micro-instructions. A single ZISC036 holds 36 neurons to implement an RBF network trained with the RCE (or ROI) algorithm.

ZISC employs Radial Basis Function (RBF) and K-Nearest Neighbor (KNN) algorithms. ZISC approach is a specialized but cheap chip to do one thing very quickly.

  • RBF: Real-valued function whose value depends only on the distance from the origin. Used as a kernel in support vector classification. Can be interpreted as a simple single-layer type of ANN.
  • KNN: Stores all avalable cases and classifies new cases based on a similarly measure (e.g. distance function). Used in statistical estimation and pattern recognition.
View ulimit.md
View cmake.md

Why CMake? Why? It is only me or do I find CMake to be convoluted and non intuitive?

  • Debug vs. Release:

Technically, this is all that is needed:

cmake -DCMAKE_BUILD_TYPE=Release ..
cmake -DCMAKE_BUILD_TYPE=Debug ..
View scala.md

Scala Notes

Variables

Immutable and mutable

Scala has two kinds of variables, vals and vars:

  • val is immutable, cannot be reassigned
  • var is mutable, can be reassigned
View riscv_debug_spec.md

Chapter 2

Each hart in the platform is controlled by exactly one DM? But, usually all harts in a single core are controlled by the same DM.

Abstract commands provide access to GPRs. Addt. registers are accessible through abstract commands or by writing to the optional program buffer.

The program buffer allows the debugger to execute arbitrary instructions on a hart. A bus access block allows memory access without using a RISC-V hart to perform the access.

Chapter 3

View primer_consistency_coherence.md

Chapter 1

Consistency models define correct shared memory behavior in terms of loads and stores without references to caches or coherence.

Chapter 2

  1. Single-Writer, Multiple-Read (Invariant): For any memory location A, at any given time, there exists only a single core that may write to A (and can also read it) ot some number of cores that may only read A.
  2. Data-Value Invariant: The value of the memory location at the start of an epoch is the same as the value of the memory location at the end of its last read-write epoch.
View shen_lipasti.md

Chapter 1

  • "Iron law": 1/Perf = time/program = instructions/program (cycle count) * cycles/instruction (CPI) * time/cycle (cycle time)
  • "Amdahl's law" = speedup = 1 / time = 1 / ((1-f)+(f/N))
    • speedup is limited by sequential bottlenec

Chapter 2

  • Three possible data dependences between two instructions, true (RAW), anti (WAR), and output (WAW). Also applies to memory data dependencies (not applicable in simple five stage pipeline).
  • There is also control dependencies.
View tilelink.md
View ddr3_features.md

Source

  • DDR3 SDRAM has eight banks, which allows more efficient interleave

Output driver impedance (Ron), ODT and ZQ calibration

  • The output driver impedence (Ron) of DQ, DQS, /DQS, and DM is selectable. Ron may fluctuate with PVR. DDR3 uses ZQ calibration.
  • ODT (On Die Termination). A termination resistor is provided by the chip to suppress signal refection. ODT resistance Rtt can be adjusted by MR2.
  • ZQ calibrate long to be issued during initialization. ZQ calibrate short to issue periodically during operation.