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edcote / oreilly_hands_on_ml.md
Last active Dec 18, 2018
Hands-On Machine Learning with Scikit & Tensor Flow Book Notes
View oreilly_hands_on_ml.md

Link to book: https://www.amazon.com/Hands-Machine-Learning-Scikit-Learn-TensorFlow/dp/1491962291

Chapter 1

ML is the field of study that gives computers the ability to learn without being explicitly programmed.

A spam filter based on ML techniques automatically learns which words and phrases are god predictors of spam by blocking unusually frequent pattern of words.

A second example where ML shines is for problems that are either too complex or have no known algorithm; speech recognition, for example.

View firewall.md

Firewall setup

Ubuntu

Official wiki has excellent documentation.

Example commands:

sudo ufw allow ssh/tcp
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edcote / llvm.md
Last active Nov 9, 2018
LLVM development notes
View llvm.md
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edcote / atom.md
Last active Nov 1, 2018
Atom editor
View atom.md
View gerrit.md
@edcote
edcote / riscvsw.md
Last active Oct 4, 2018
RISC-V System Software
View riscvsw.md

RISC-V System Software

Ignore the instructions to build GCC/Newlib toolchain. Consult this Linux/RISC-V installation manual instead.

Setup environment variables

module load riscv-tools/local

# old
export RISCV_SW=$CAD_ROOT/riscv-sw
View riscv_debug_spec.md

Chapter 2

Each hart in the platform is controlled by exactly one DM? But, usually all harts in a single core are controlled by the same DM.

Abstract commands provide access to GPRs. Addt. registers are accessible through abstract commands or by writing to the optional program buffer.

The program buffer allows the debugger to execute arbitrary instructions on a hart. A bus access block allows memory access without using a RISC-V hart to perform the access.

Chapter 3

@edcote
edcote / riscv-user.md
Created May 26, 2018
RISC-V User-Level ISA
View riscv-user.md

Base

  • ISA separated into small base ISA and support for extensions
  • JAL stores the address of the instruction following the jump (pc+4) into register rd. Calling convention is x1 as return address and x5 as alternate link register. Return address stack can be manipulated by JAL/JALR.
  • Aligned loads and stores are guaranteed to execute atomically, misaligned loads and stores are not
  • Each hart observes its own memory operations as if they are executed in sequential program order. RISC-V observes a relaxed memory model between harts. Explicit FENCE instructions are required to guarantee ordering between memory operations from different harts.
  • FENCE is used to order I/O and memory accesses as viewed by other RISC-V harts, external devices, and co-processors. No other hart or external device can observe any operation in the successor set following a FENCE operation before any operation in the predecessor set before the FENCE.

Atomic "A"

@edcote
edcote / boomv2.md
Last active Oct 3, 2018
BOOM v2: An Open-Source OoO RISC-V Core
View boomv2.md

Notes

Link to tech report

Alpha 21264 has 15 FO4 delays. (FO4 delay is the delay of inverter, driven by an inverter 4x smaller than itself, and driving an interter 4x bigger than itself). BOOMv2 is 35 FO4.

BOOMv1 follows the 6-stage pipeline structure of MIPS R10K - fetch, decode/rename, issue/register-read, excute, memory, and writeback.

Frontend fetches instructions for execution in the backend.

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edcote / jenkins_docker.md
Last active Oct 3, 2018
Jenkins and Docker
View jenkins_docker.md

Goal

  • To deploy riscv-ci on docker, with preserved data.

    mkdir -p docker/riscv-ci cd docker/riscv-ci

Docker and Jenkins setup

  • Create an image on top of the Jenkins image with log, cache directories and java opts
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