Link to FIRRTL specification here
All FIRRTL circuits consist of a list of modules. Each module as a name, list of ports, and statements.
Types are used to specify the structure of data. Here are examples:
- Integer: UInt<10>, SInt<32>
- Clock: Clock
- Vectors: UInt<16>[10]
- Bundles: {real: SInt<10>, img:SInt<10>}, {valid: UInt<1>, flipped ready: UInt<1>}
Here is example of a connect statement:
module MyModule :
input myinput: UInt
output myoutput: UInt
myoutput <= myinput
FIRRTL supports the notion of partial connection where sign extension or truncation is automatically inferred.
Wires and registers are declared as such:
wire mywire : UInt
wire myclock : Clock
reg myreg: SInt, myclock
Invalidates are used to that a circuit component indeterminant values.
Nodes are named intermediate values in a circuit.
wire pred: UInt<1>
wire a: SInt
wire b: SInt
node mynode = mux(pred, a, b)
Conditionals connection occur when the given condition is high. The condition must have a 1-bit unsigned data type.
module MyModule :
input a: UInt
input b: UInt
input en: UInt<1>
wire x: UInt
when en :
x <= a
else :
x <= b