from https://github.com/EECS150/fpga_project_skeleton_fa22/blob/master/hardware/src/io_circuits/fifo.v
module fifo #(
parameter WIDTH = 32, // data width is 32-bit
parameter LOGDEPTH = 3 // 2^3 = 8 entries
) (
input clk,
from https://github.com/EECS150/fpga_project_skeleton_fa22/blob/master/hardware/src/io_circuits/fifo.v
module fifo #(
parameter WIDTH = 32, // data width is 32-bit
parameter LOGDEPTH = 3 // 2^3 = 8 entries
) (
input clk,