Created
October 4, 2021 15:19
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7-Series ICAPE2 Registers Write/Read test.
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#!/usr/bin/env python3 | |
import sys | |
import argparse | |
from litex import RemoteClient | |
from litex.soc.cores.icap import * | |
# Add the ICAP module to your 7-Series LiteX SoC: | |
# from litex.soc.cores.icap import ICAP | |
# self.submodules.icap = ICAP() | |
# self.icap.add_csr() | |
# self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) | |
# IPROG Test --------------------------------------------------------------------------------------- | |
def iprog_test(port): | |
bus = RemoteClient(port=port, csr_csv="csr.csv") | |
bus.open() | |
bus.regs.icap_addr.write(ICAPRegisters.CMD) | |
bus.regs.icap_data.write(ICAPCMDs.IPROG) | |
bus.regs.icap_write.write(1) | |
while (bus.regs.icap_done.read() == 0): | |
pass | |
bus.regs.icap_write.write(0) | |
bus.close() | |
# Dump Test -------------------------------------------------------------------------------------- | |
def dump_test(port): | |
bus = RemoteClient(port=port, csr_csv="csr.csv") | |
bus.open() | |
for reg in ICAPRegisters: | |
bus.regs.icap_addr.write(reg.value) | |
bus.regs.icap_read.write(1) | |
while (bus.regs.icap_done.read() == 0): | |
pass | |
bus.regs.icap_read.write(0) | |
print(f"{reg.name}{' '*(20-len(reg.name))}: 0x{bus.regs.icap_data.read():08x}") | |
bus.close() | |
# Run ---------------------------------------------------------------------------------------------- | |
def main(): | |
parser = argparse.ArgumentParser(description="LiteX ICAPE2 test utility") | |
parser.add_argument("--port", default="1234", help="Host bind port") | |
parser.add_argument("--iprog", action="store_true", help="Test IPROG") | |
parser.add_argument("--dump", action="store_true", help="Test Dump") | |
args = parser.parse_args() | |
port = int(args.port, 0) | |
if args.iprog: | |
iprog_test(port=port) | |
if args.dump: | |
dump_test(port=port) | |
if __name__ == "__main__": | |
main() |
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