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@enjoy-digital
enjoy-digital / axi_converter.py
Created April 6, 2022 08:32
AXI-Stream Converter from LiteX's Converter.
#!/usr/bin/env python3
import os
import shutil
import argparse
from migen import *
from litex.build import tools
from litex.build.generic_platform import *
@enjoy-digital
enjoy-digital / arty.py
Last active January 27, 2022 22:37
LiteEth Interboard demo between Arty and Butterstick
#!/usr/bin/env python3
# LiteEth UDP Inter-board stream demo.
#
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# ./arty.py --build --load
import os
@enjoy-digital
enjoy-digital / litejesd204b_integration_example.py
Created November 30, 2021 15:04
LiteJESD204B integration example on Xilinx 7-Series.
from functools import reduce
from operator import and_
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import DifferentialInput
from litex.soc.cores.clock import S7MMCM
@enjoy-digital
enjoy-digital / test_ws2812.py
Created November 4, 2021 14:46
WS2812/NeoPixel LiteX core test over Bridge.
#!/usr/bin/env python3
import time
from litex import RemoteClient
bus = RemoteClient()
bus.open()
# # #
@enjoy-digital
enjoy-digital / usb_cdc.py
Created October 19, 2021 20:19
Ultraembedded's USB CDC Device LiteX wrapper
#
# This file is part of LiteX.
#
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# Ultraembedded's USB CDC Device LiteX wrapper:
# USB CDC Core: https://github.com/ultraembedded/core_usb_cdc
# UMTI <> ULPI Core: https://github.com/ultraembedded/core_ulpi_wrapper
@enjoy-digital
enjoy-digital / si5324_i2c.py
Created October 14, 2021 14:12
KC705 PCA9548 + Si5324 (122.88MHz) I2C configuration
from collections import namedtuple
from migen import *
from litex.soc.interconnect import wishbone
# I2C-----------------------------------------------------------------------------------------------
class I2CClockGen(Module):
def __init__(self, width):
@enjoy-digital
enjoy-digital / test_icap.py
Created October 4, 2021 15:19
7-Series ICAPE2 Registers Write/Read test.
#!/usr/bin/env python3
import sys
import argparse
from litex import RemoteClient
from litex.soc.cores.icap import *
# Add the ICAP module to your 7-Series LiteX SoC:
@enjoy-digital
enjoy-digital / sdram_init.py
Last active July 22, 2021 20:28
DRAM initialization through Wishbone FSM.
#!/usr/bin/env python3
from migen import *
from wb_master import *
from wb_master import _WRITE_CMD, _WAIT_CMD, _DONE_CMD
dfii_control_sel = 0x01
dfii_control_cke = 0x02
dfii_control_odt = 0x04
@enjoy-digital
enjoy-digital / digilent_arty_s7.py
Created June 11, 2021 07:36
Add Ethernet to your SoC with cheap Lan8720 RMII "PMOD"
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>,
# Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
# SPDX-License-Identifier: BSD-2-Clause
import os
@enjoy-digital
enjoy-digital / tec0117.py
Created April 30, 2021 17:09
Raspberry Pi Pico <> LiteX SoC (on GoWin FPGA) proof of concept.
#!/usr/bin/env python3
# Raspberry Pi Pico <> LiteX SoC (on GoWin FPGA) proof of concept.
#
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse