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/* Machine-generated using LiteX gen */ | |
module top( | |
output reg serial_tx, | |
input serial_rx, | |
input clk100, | |
input cpu_reset, | |
output eth_ref_clk, | |
output [13:0] ddram_a, | |
output [2:0] ddram_ba, | |
output ddram_ras_n, |
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