forensicgarlic

always @ (posedge clk)
begin
  // the below runs into problems because apparently the cnt value
  // is evaluated after addition instead of the registered version.
  // changing cnt <= cnt + 1 to cnt = cnt + 1 had no effect. 
  //if (cnt == max_value) begin
  //   results_valid <= 1;
  //end else if (accum3 | accum5) begin
  //   results <= results + cnt;
  //end

forensicgarlic

module myInvert(a,b);

   input wire a;
   output wire b;

   assign b = !a;
endmodule // myInvert

forensicgarlic

// Code generated by Icestudio 0.3.0-beta3
// Wed, 22 Mar 2017 19:04:57 GMT

`default_nettype none

module main #(
 parameter vb768ba = 4'h2,
 parameter vd39cf6 = 4'h5,
 parameter v8a74c9 = 12000000
) (

forensicgarlic

EULER3_A: process (clk, reset) is
begin
    if (reset = '1') then
        y <= to_unsigned(1, 64);
        x <= to_unsigned(1, 64);
        product <= to_unsigned(1, 64);
        roots <= to_unsigned(1, 64);
    elsif rising_edge(clk) then
        if (bool(enable) and (not bool(results_valid_int))) then
            if ((y mod x) = 0) then

forensicgarlic

    @always_seq(clk.posedge, reset)
    def a():
      if enable and not results_valid_int:
        if (y % x == 0):
          roots.next = x
          product.next = product * x
          y.next = y // x
        else:
          x.next = x + 1
        elif not enable:

forensicgarlic

    def euler3_py(self, number):
      roots = 0
      product = 1
      x = 2
      y = number
      while product != number:
        while (y % x == 0):
          roots = x
          y /= x
          product *= roots

forensicgarlic

HARDWAY2_HARDHEADED2: process (clk, reset) is
    variable f1: integer;
    variable f2: integer;
    variable f1_old: std_logic;
    variable results_int: integer;
begin
    if (reset = '1') then
        results_valid <= '0';
        results <= to_unsigned(0, 64);
    elsif rising_edge(clk) then

forensicgarlic

    @always_seq(clk.posedge, reset)
    def hardheaded2():
        f1 = 1
        f2 = 1
        results_int = 0
        while (f1 + f2) < max_value:
            results_int = results_int + f1 + f2
            #tuple assignment is not supported in hardware conversion
            #f1, f2 = f1 + (2 * f2), (2 * f1) + (3 * f2)
            #if these were signals, I wouldn't be worried about the below being sequential. Since they aren't though...

forensicgarlic

    def checkResultHw(self):
        self.reset.next = 1
        yield self.clk.negedge
        self.reset.next = 0

        print "set and check 100"
        #you can't call the function like
        #self.set_and_check(100)
        #instead you have to yield to it because it's a myHDL generator.
        yield self.set_and_check(100)

forensicgarlic

    def set_and_check(self, max_value):
         print "in set and check"
         self.max_value.next = max_value;
         yield self.clk.negedge
         self.enable.next = True
         yield self.results_valid
         print "expected results = %d" % self.euler2_py(self.max_value)
         print "actual results   = %d" % self.results
         self.assertEqual(self.results, self.euler2_py(self.max_value),
                              "does " + str(self.results) + " == " + str(self.euler2_py(self.max_value)) + " for max == " + str(self.max_value))