VHDL converted from python automatically for euler problem 3

convertedPythonToVHDL.vhd

EULER3_A: process (clk, reset) is
begin
    if (reset = '1') then
        y <= to_unsigned(1, 64);
        x <= to_unsigned(1, 64);
        product <= to_unsigned(1, 64);
        roots <= to_unsigned(1, 64);
    elsif rising_edge(clk) then
        if (bool(enable) and (not bool(results_valid_int))) then
            if ((y mod x) = 0) then
                roots <= x;
                product <= resize(product * x, 64);
                y <= (y / x);
            else
                x <= (x + 1);
            end if;
        elsif (not bool(enable)) then
            roots <= to_unsigned(0, 64);
            product <= to_unsigned(1, 64);
            x <= to_unsigned(2, 64);
            y <= max_value;
        end if;
    end if;
end process EULER3_A;