作ったはいいけど思った通りの動作をしてくれない子。馬鹿な子ほど可愛いというけれども……

stack.v

// module stack
// it is submodule of pc
module stack(clk, en, pu_po, qi, qo);
   parameter WIDTH = 9;
   
   input clk, en, pu_po;
   input [WIDTH-1:0] qi;

   output [WIDTH-1:0] qo;
   
   reg [WIDTH-1:0]    qo;

   reg [WIDTH-1:0]    s1,s2;

   always @(posedge clk) begin
      if((en == 1) && (pu_po == 1)) 
         s2 <= s1;
      else
         s2 <= s2;
   end
   
   always @(posedge clk) begin
      if((en == 1) && (pu_po == 1))
         s1 <= qi;
      else if((en == 1) && (pu_po == 0)) 
         s1 <= s2;
      else
         s1 <= s1;
   end
   
   always @(posedge clk) begin
      if((en == 1) && (pu_po == 0))
         qo <= s1;
      else
         qo <= qo;
   end
   
   initial qo <= 0;
   
endmodule // stack

stack_tb.v

// module stack_tp
// test bench for stack module.
`timescale 1ms/1ms
module stack_tp;

   parameter WIDTH = 9;
   parameter STEP = 10;

   wire [WIDTH-1:0] qo;
   reg [WIDTH-1:0]  qi;
   reg 		    en,pu_po;
   reg 		    clk;

   stack stack0(clk, en, pu_po, qi, qo);

   always begin
      #(STEP/2) clk = 1;
      #(STEP/2) clk = 0;
   end

   initial begin
      $dumpfile("stack.vcd");
      $dumpvars(0, stack0);
      $monitor("en: %b, pu_po: %b, qi: %h, qo: %h",en, pu_po, qi, qo);
   end

   initial begin
      en <= 1;
      pu_po <= 1;
      qi <= 9'h13f;
      repeat (1) @(posedge clk);
      en <= 1;
      qi <= 9'h03d;
      repeat (1) @(posedge clk);
      pu_po <= 0;
      en <= 1;
      repeat (2) @(posedge clk);
      en <= 1;
      pu_po <= 1;
      qi <= 9'h099;
      repeat (1) @(posedge clk);      
      en <= 1;
      pu_po <= 0;
      repeat (1) @(posedge clk);
      en <= 1;
      pu_po <= 1;
      qi <= 9'h077;
      repeat (1) @(posedge clk);      
      $finish;
   end // initial begin

endmodule // stack_tp