Created
August 8, 2019 15:24
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FMCOMMS5 Clock
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| clock enable_cnt prepare_cnt rate accuracy phase | |
| ---------------------------------------------------------------------------------------- | |
| spi0.1-tx_lo_dummy 0 0 1200000000 0 0 | |
| spi0.1-rx_lo_dummy 0 0 1200000000 0 0 | |
| spi0.0-tx_lo_dummy 0 0 1200000000 0 0 | |
| spi0.0-rx_lo_dummy 0 0 1200000000 0 0 | |
| clock-generator3 0 0 148499999 0 0 | |
| clock-generator2 0 0 299999997 0 0 | |
| ad9361_ext_refclk 8 8 10000000 0 0 | |
| spi0.1-bb_refclk 1 1 20000000 0 0 | |
| spi0.1-bbpll_clk 1 1 960000000 0 0 | |
| spi0.1-adc_clk 1 1 480000000 0 0 | |
| spi0.1-dac_clk 1 1 240000000 0 0 | |
| spi0.1-t2_clk 1 1 120000000 0 0 | |
| spi0.1-t1_clk 1 1 60000000 0 0 | |
| spi0.1-clktf_clk 1 1 60000000 0 0 | |
| spi0.1-tx_sampl_clk 1 1 60000000 0 0 | |
| spi0.1-r2_clk 0 0 240000000 0 0 | |
| spi0.1-r1_clk 0 0 120000000 0 0 | |
| spi0.1-clkrf_clk 0 0 60000000 0 0 | |
| spi0.1-rx_sampl_clk 0 0 60000000 0 0 | |
| spi0.1-rx_refclk 1 1 20000000 0 0 | |
| spi0.1-rx_rfpll_int 1 1 1200000000 0 0 | |
| spi0.1-rx_rfpll 1 1 1200000000 0 0 | |
| spi0.1-tx_refclk 1 1 20000000 0 0 | |
| spi0.1-tx_rfpll_int 1 1 1200000000 0 0 | |
| spi0.1-tx_rfpll 1 1 1200000000 0 0 | |
| spi0.0-bb_refclk 1 1 20000000 0 0 | |
| spi0.0-bbpll_clk 1 1 960000000 0 0 | |
| spi0.0-adc_clk 1 1 480000000 0 0 | |
| spi0.0-dac_clk 1 1 240000000 0 0 | |
| spi0.0-t2_clk 1 1 120000000 0 0 | |
| spi0.0-t1_clk 1 1 60000000 0 0 | |
| spi0.0-clktf_clk 1 1 60000000 0 0 | |
| spi0.0-tx_sampl_clk 1 1 60000000 0 0 | |
| spi0.0-r2_clk 0 0 240000000 0 0 | |
| spi0.0-r1_clk 0 0 120000000 0 0 | |
| spi0.0-clkrf_clk 0 0 60000000 0 0 | |
| spi0.0-rx_sampl_clk 0 0 60000000 0 0 | |
| spi0.0-rx_refclk 1 1 20000000 0 0 | |
| spi0.0-rx_rfpll_int 1 1 606299998 0 0 | |
| spi0.0-rx_rfpll 1 1 606299998 0 0 | |
| spi0.0-tx_refclk 1 1 20000000 0 0 | |
| spi0.0-tx_rfpll_int 1 1 1200000000 0 0 | |
| spi0.0-tx_rfpll 1 1 1200000000 0 0 | |
| dp_aclk 1 1 100000000 100 0 | |
| aux_ref_clk 0 0 27000000 0 0 | |
| gt_crx_ref_clk 0 0 108000000 0 0 | |
| pss_alt_ref_clk 0 0 0 0 0 | |
| video_clk 0 0 27000000 0 0 | |
| pss_ref_clk 3 3 33330000 0 0 | |
| vpll_post_src 0 0 33330000 0 0 | |
| vpll_pre_src 0 0 33330000 0 0 | |
| vpll_int 0 0 2999700000 0 0 | |
| vpll_half 0 0 1499850000 0 0 | |
| vpll_int_mux 0 0 1499850000 0 0 | |
| vpll 0 0 1499850000 0 0 | |
| dp_video_ref_mux 0 0 1499850000 0 0 | |
| dp_video_ref_div1 0 0 299970000 0 0 | |
| dp_video_ref_div2 0 0 299970000 0 0 | |
| dp_video_ref 0 0 299970000 0 0 | |
| vpll_to_lpd 0 0 499950000 0 0 | |
| dpll_post_src 0 0 33330000 0 0 | |
| dpll_pre_src 0 0 33330000 0 0 | |
| dpll_int 0 0 2133120000 0 0 | |
| dpll_half 0 0 1066560000 0 0 | |
| dpll_int_mux 0 0 1066560000 0 0 | |
| dpll 0 0 1066560000 0 0 | |
| dpll_to_lpd 0 0 533280000 0 0 | |
| apll_post_src 0 0 33330000 0 0 | |
| apll_pre_src 1 1 33330000 0 0 | |
| apll_int 1 1 2399760000 0 0 | |
| apll_half 1 1 1199880000 0 0 | |
| apll_int_mux 1 1 1199880000 0 0 | |
| apll 1 1 1199880000 0 0 | |
| dpdma_ref_mux 1 1 1199880000 0 0 | |
| dpdma_ref_div1 1 1 599940000 0 0 | |
| dpdma_ref 1 1 599940000 0 0 | |
| gdma_ref_mux 0 0 1199880000 0 0 | |
| gdma_ref_div1 0 0 599940000 0 0 | |
| gdma_ref 0 0 599940000 0 0 | |
| acpu_mux 0 0 1199880000 0 0 | |
| acpu 0 0 1199880000 0 0 | |
| rpll_post_src 0 0 33330000 0 0 | |
| rpll_pre_src 1 1 33330000 0 0 | |
| rpll_int 1 1 2408447994 0 0 | |
| rpll_half 1 1 1204223997 0 0 | |
| rpll_int_mux 1 1 1204223997 0 0 | |
| rpll 2 2 1204223997 0 0 | |
| spi1_ref_mux 0 0 1204223997 0 0 | |
| spi1_ref_div1 0 0 100352000 0 0 | |
| spi1_ref_div2 0 0 100352000 0 0 | |
| spi1_ref 0 0 100352000 0 0 | |
| spi0_ref_mux 1 1 1204223997 0 0 | |
| spi0_ref_div1 1 1 100352000 0 0 | |
| spi0_ref_div2 1 1 100352000 0 0 | |
| spi0_ref 1 1 100352000 0 0 | |
| rpll_to_fpd 1 1 24576000 0 0 | |
| dp_stc_ref_mux 0 0 24576000 0 0 | |
| dp_stc_ref_div1 0 0 1638400 0 0 | |
| dp_stc_ref_div2 0 0 1638400 0 0 | |
| dp_stc_ref 0 0 1638400 0 0 | |
| dp_audio_ref_mux 1 1 24576000 0 0 | |
| dp_audio_ref_div1 1 1 24576000 0 0 | |
| dp_audio_ref_div2 1 1 24576000 0 0 | |
| dp_audio_ref 1 1 24576000 0 0 | |
| iopll_post_src 0 0 33330000 0 0 | |
| iopll_pre_src 1 1 33330000 0 0 | |
| iopll_int 1 1 2999700000 0 0 | |
| iopll_half 1 1 1499850000 0 0 | |
| iopll_int_mux 1 1 1499850000 0 0 | |
| iopll 10 14 1499850000 0 0 | |
| gem3_ref_ung_mux 1 1 1499850000 0 0 | |
| gem3_ref_ung_div1 1 1 124987500 0 0 | |
| gem3_ref_ung 1 1 124987500 0 0 | |
| gem3_ref 2 2 124987500 0 0 | |
| gem3_tx 1 1 124987500 0 0 | |
| gem2_ref_ung_mux 0 0 1499850000 0 0 | |
| gem2_ref_ung_div1 0 0 62493750 0 0 | |
| gem2_ref_ung 0 0 62493750 0 0 | |
| gem2_ref 0 0 62493750 0 0 | |
| gem2_tx 0 0 62493750 0 0 | |
| gem1_ref_ung_mux 0 0 1499850000 0 0 | |
| gem1_ref_ung_div1 0 0 62493750 0 0 | |
| gem1_ref_ung 0 0 62493750 0 0 | |
| gem1_ref 0 0 62493750 0 0 | |
| gem1_tx 0 0 62493750 0 0 | |
| gem0_ref_ung_mux 0 0 1499850000 0 0 | |
| gem0_ref_ung_div1 0 0 62493750 0 0 | |
| gem0_ref_ung 0 0 62493750 0 0 | |
| gem0_ref 0 0 62493750 0 0 | |
| gem0_tx 0 0 62493750 0 0 | |
| pl3_ref_mux 0 0 1499850000 0 0 | |
| pl3_ref_div1 0 0 46870313 0 0 | |
| pl3_ref_div2 0 0 9374063 0 0 | |
| pl3_ref 0 0 9374063 0 0 | |
| pl2_ref_mux 1 1 1499850000 0 0 | |
| pl2_ref_div1 1 1 499950000 0 0 | |
| pl2_ref_div2 1 1 499950000 0 0 | |
| pl2_ref 3 3 499950000 0 0 | |
| pl1_ref_mux 0 0 1499850000 0 0 | |
| pl1_ref_div1 0 0 249975000 0 0 | |
| pl1_ref_div2 0 0 249975000 0 0 | |
| pl1_ref 0 0 249975000 0 0 | |
| pl0_ref_mux 1 1 1499850000 0 0 | |
| pl0_ref_div1 1 1 99990000 0 0 | |
| pl0_ref_div2 1 1 99990000 0 0 | |
| pl0_ref 1 1 99990000 0 0 | |
| ams_ref_mux 1 1 1499850000 0 0 | |
| ams_ref_div1 1 1 49995000 0 0 | |
| ams_ref_div2 1 1 49995000 0 0 | |
| ams_ref 1 1 49995000 0 0 | |
| adma_ref_mux 0 0 1499850000 0 0 | |
| adma_ref_div1 0 0 499950000 0 0 | |
| adma_ref 0 0 499950000 0 0 | |
| can1_ref_mux 0 0 1499850000 0 0 | |
| can1_ref_div1 0 0 99990000 0 0 | |
| can1_ref_div2 0 0 99990000 0 0 | |
| can1_ref 0 0 99990000 0 0 | |
| can1 0 0 99990000 0 0 | |
| can0_ref_mux 0 0 1499850000 0 0 | |
| can0_ref_div1 0 0 46870313 0 0 | |
| can0_ref_div2 0 0 46870313 0 0 | |
| can0_ref 0 0 46870313 0 0 | |
| can0 0 0 46870313 0 0 | |
| i2c1_ref_mux 0 1 1499850000 0 0 | |
| i2c1_ref_div1 0 1 99990000 0 0 | |
| i2c1_ref_div2 0 1 99990000 0 0 | |
| i2c1_ref 0 1 99990000 0 0 | |
| i2c0_ref_mux 0 1 1499850000 0 0 | |
| i2c0_ref_div1 0 1 99990000 0 0 | |
| i2c0_ref_div2 0 1 99990000 0 0 | |
| i2c0_ref 0 1 99990000 0 0 | |
| nand_ref_mux 0 0 1499850000 0 0 | |
| nand_ref_div1 0 0 46870313 0 0 | |
| nand_ref_div2 0 0 9374063 0 0 | |
| nand_ref 0 0 9374063 0 0 | |
| uart1_ref_mux 0 1 1499850000 0 0 | |
| uart1_ref_div1 0 1 99990000 0 0 | |
| uart1_ref_div2 0 1 99990000 0 0 | |
| uart1_ref 0 1 99990000 0 0 | |
| uart0_ref_mux 1 1 1499850000 0 0 | |
| uart0_ref_div1 1 1 99990000 0 0 | |
| uart0_ref_div2 1 1 99990000 0 0 | |
| uart0_ref 1 1 99990000 0 0 | |
| sdio1_ref_mux 1 1 1499850000 0 0 | |
| sdio1_ref_div1 1 1 187481250 0 0 | |
| sdio1_ref_div2 1 1 187481250 0 0 | |
| sdio1_ref 1 1 187481250 0 0 | |
| sdio0_ref_mux 0 0 1499850000 0 0 | |
| sdio0_ref_div1 0 0 99990000 0 0 | |
| sdio0_ref_div2 0 0 99990000 0 0 | |
| sdio0_ref 0 0 99990000 0 0 | |
| qspi_ref_mux 0 1 1499850000 0 0 | |
| qspi_ref_div1 0 1 124987500 0 0 | |
| qspi_ref_div2 0 1 124987500 0 0 | |
| qspi_ref 0 1 124987500 0 0 | |
| gem_tsu_ref_mux 1 1 1499850000 0 0 | |
| gem_tsu_ref_div1 1 1 249975000 0 0 | |
| gem_tsu_ref_div2 1 1 249975000 0 0 | |
| gem_tsu_ref 1 1 249975000 0 0 | |
| gem_tsu 1 1 249975000 0 0 | |
| usb3_dual_ref_mux 1 1 1499850000 0 0 | |
| usb3_dual_ref_div1 1 1 59994000 0 0 | |
| usb3_dual_ref_div2 1 1 19998000 0 0 | |
| usb3_dual_ref 1 1 19998000 0 0 | |
| usb1_bus_ref_mux 0 0 1499850000 0 0 | |
| usb1_bus_ref_div1 0 0 124987500 0 0 | |
| usb1_bus_ref_div2 0 0 124987500 0 0 | |
| usb1_bus_ref 0 0 124987500 0 0 | |
| usb0_bus_ref_mux 1 1 1499850000 0 0 | |
| usb0_bus_ref_div1 1 1 249975000 0 0 | |
| usb0_bus_ref_div2 1 1 249975000 0 0 | |
| usb0_bus_ref 1 1 249975000 0 0 | |
| iopll_to_fpd 3 3 499950000 0 0 | |
| topsw_lsbus_mux 1 1 499950000 0 0 | |
| topsw_lsbus_div1 1 1 99990000 0 0 | |
| topsw_lsbus 1 1 99990000 0 0 | |
| wdt 2 2 99990000 0 0 | |
| gpu_ref_mux 0 0 499950000 0 0 | |
| gpu_ref_div1 0 0 499950000 0 0 | |
| gpu_ref 0 0 499950000 0 0 | |
| gpu_pp1_ref 0 0 499950000 0 0 | |
| gpu_pp0_ref 0 0 499950000 0 0 | |
| pcie_ref_mux 1 1 499950000 0 0 | |
| pcie_ref_div1 1 1 249975000 0 0 | |
| pcie_ref 1 1 249975000 0 0 | |
| sata_ref_mux 1 1 499950000 0 0 | |
| sata_ref_div1 1 1 249975000 0 0 | |
| sata_ref 1 1 249975000 0 0 | |
| can1_mio 0 0 0 0 0 | |
| can0_mio 0 0 0 0 0 | |
| gem3_rx 1 1 0 0 0 | |
| gem2_rx 0 0 0 0 0 | |
| gem1_rx 0 0 0 0 0 | |
| gem0_rx 0 0 0 0 0 |
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