dpram yosys test script

#ghdl pck_myhdl_011.vhd test_dpram_tdp_r2w1_ce.vhd -e test_dpram_tdp_r2w1_ce
read_verilog test_dpram_tdp_r2w1_ce.v
read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v
hierarchy -check -top test_dpram_tdp_r2w1_ce
show -prefix pre
proc
flatten
tribuf -logic
deminout
synth -run coarse
# memory_collect
memory_bram -rules brams.txt
techmap -map ecp5/brams_map.v
show -prefix map

Example TDP 2R1W

// File: test_dpram_tdp_r2w1.v
// Generated by MyHDL 0.11
// Date: Thu Feb 27 18:01:47 2020


`timescale 1ns/10ps

module test_dpram_tdp_r2w1 (
    clk,
    addr,
    we,
    check,
    a_we,
    a_addr,
    a_clk,
    a_read,
    a_ce,
    a_write,
    b_we,
    b_addr,
    b_clk,
    b_read,
    b_ce,
    b_write
);
// Entities that are 'required' to work

input clk;
input [7:0] addr;
input we;
output [3:0] check;
reg [3:0] check;
input a_we;
input [7:0] a_addr;
input a_clk;
output [15:0] a_read;
reg [15:0] a_read;
input a_ce;
input [15:0] a_write;
input b_we;
input [7:0] b_addr;
input b_clk;
output [15:0] b_read;
reg [15:0] b_read;
input b_ce;
input [15:0] b_write;

reg pb_clk;
reg pb_we;
reg pa_clk;
reg [15:0] pa_write;
wire [15:0] pb_read;
reg [15:0] pb_write;
reg pa_we;
reg [7:0] pa_addr;
reg [7:0] pb_addr;
wire [15:0] pa_read;
reg [15:0] dpram_tdp_r2w10_mem [0:256-1];

assign pb_read = 16'd0;
assign pa_read = 16'd0;


always @(we, clk, b_addr, a_addr, b_write, pb_read, a_write, pa_read) begin: TEST_DPRAM_TDP_R2W1_ASSIGN
    pa_clk = clk;
    pb_clk = clk;
    pa_addr = a_addr;
    pb_addr = b_addr;
    pa_write = a_write;
    pb_write = b_write;
    pa_we = we;
    pb_we = we;
    if (0) begin
        if ((pa_read == 64206)) begin
            check = 0;
        end
        else begin
            check = 1;
        end
        if ((pb_read == 64206)) begin
            check = 2;
        end
        else begin
            check = 3;
        end
    end
end


always @(posedge a_clk) begin: TEST_DPRAM_TDP_R2W1_DPRAM_TDP_R2W10_PORTA_PROC
    if (a_we) begin
        dpram_tdp_r2w10_mem[a_addr] <= a_write;
        a_read <= a_write;
    end
    else begin
        a_read <= dpram_tdp_r2w10_mem[a_addr];
    end
end


always @(posedge b_clk) begin: TEST_DPRAM_TDP_R2W1_DPRAM_TDP_R2W10_PORTB_PROC
    b_read <= dpram_tdp_r2w10_mem[b_addr];
end

endmodule

test_dpram_tdp_r2w1.vhdl

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_011.all;

entity test_dpram_tdp_r2w1 is
    port (
        clk: in std_logic;
        addr: in unsigned(11 downto 0);
        we: in std_logic;
        check: out unsigned(3 downto 0);
        a_we: in std_logic;
        a_addr: in unsigned(11 downto 0);
        a_clk: in std_logic;
        a_read: out unsigned(15 downto 0);
        a_ce: in std_logic;
        a_write: in unsigned(15 downto 0);
        b_we: in std_logic;
        b_addr: in unsigned(11 downto 0);
        b_clk: in std_logic;
        b_read: out unsigned(15 downto 0);
        b_ce: in std_logic;
        b_write: in unsigned(15 downto 0)
    );
end entity test_dpram_tdp_r2w1;
-- Entities that are 'required' to work

architecture MyHDL of test_dpram_tdp_r2w1 is


type t_array_dpram_tdp_r2w10_mem is array(0 to 4096-1) of unsigned(15 downto 0);
signal dpram_tdp_r2w10_mem: t_array_dpram_tdp_r2w10_mem;

begin


TEST_DPRAM_TDP_R2W1_DPRAM_TDP_R2W10_PORTA_PROC: process (a_clk) is
begin
    if rising_edge(a_clk) then
        if bool(a_we) then
            dpram_tdp_r2w10_mem(to_integer(a_addr)) <= a_write;
        else
            a_read <= dpram_tdp_r2w10_mem(to_integer(a_addr));
        end if;
    end if;
end process TEST_DPRAM_TDP_R2W1_DPRAM_TDP_R2W10_PORTA_PROC;

TEST_DPRAM_TDP_R2W1_DPRAM_TDP_R2W10_PORTB_PROC: process (b_clk) is
begin
    if rising_edge(b_clk) then
        b_read <= dpram_tdp_r2w10_mem(to_integer(b_addr));
    end if;
end process TEST_DPRAM_TDP_R2W1_DPRAM_TDP_R2W10_PORTB_PROC;

end architecture MyHDL;

Important to note: Needs the proper read-after-write 'spelling', see: YosysHQ/yosys#1087

This is what should be expected:

When doing it wrong, you'll get this:

I.e. one read port will be synchronous, one asynchronous, instead of b_clk wired to the read clock as well.
GHDL will currently produce the correct result for a read-before-write translation, however it may not map correctly to the ECP5 primitive.

For a writethrough emulation, you might also get the above wrong result with one asychronous read port