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heejongahn / .travis.yml
Created Aug 28, 2019
Flutter 배포 자동화: iOS가 완료된 시점
View .travis.yml
# .travis.yml
language: generic
- FLUTTER_BUILD_RELEASE_CHANNEL=stable # 사용할 빌드 릴리즈 채널
- name: iOS Build
os: osx
View keybindings.json
// Place your key bindings in this file to overwrite the defaults
"key": "cmd+3",
"command": "editor.action.goToDeclaration",
"when": "editorHasDefinitionProvider && editorTextFocus && !isInEmbeddedEditor"
"key": "cmd+4",
"command": "workbench.action.navigateBack"
heejongahn /
Last active Feb 8, 2017
hjlog 이미지 S3 이주 대작전
import re
from hjlog import db
from hjlog.models import Post
S3_BASE_URL = ''
pattern = re.compile('!\[(.*)\]\(/static/image/photo/(.*)\)')
def repl(m):
View errorMsg
No instance for (MonadRandom Vector)
arising from a use of ‘getRandomR’
In a stmt of a 'do' block: victim <- getRandomR (0, i)
In the expression:
do { victim <- getRandomR (0, i);
(unsafeSwapV i victim v) }
In an equation for ‘shuffleStep’:
shuffleStep v i
= do { victim <- getRandomR (0, i);
View fix.hs
configFish <- catchIOError (B.readFile configFishPath)
(\ e -> if isDoesNotExistError e
then do
B.writeFile configFishPath B.empty
return ""
else ioError e)
heejongahn /
Last active Dec 14, 2015
2015 Fall 아키텍쳐 기말

1. Mark whether each of the following statements is true or false.

A. Increasing the block size of a cache always reduces the cache miss rate by increasing the chance to exploit spatial locality. [ T / F ]

False. 블락 사이즈가 너무 커지면 캐시 블락이 몇 개 못 들어가서 miss rate가 높아짐.

B. Increasing the cache size does not reduce coherence misses in shared memory multiprocessors. [T/F]

True. 캐시에 들어있는게 많으니까 invalidation이 늘어남.

C. Increasing the block size does not increase coherence misses in shared memory multiprocessors. [ T / F ]

False. 여러 프로세스가 한 블락에 접근할 확률이 높아서져 coherence miss 증가.

heejongahn /
Last active Oct 29, 2015
Midterm prep


1-1. The CPI of a single cycle design is always less than or equal to the CPI of a pipelined implementation.

True. singly cycle design 에서 CPI는 무조건 1. 파이프라인에서는 ideally 1, 실제로는 더 커질 수 있음.

1-2. Since RISC can access the memory only through load and store instructions, RISC must support many different addressing modes to satisfy various memory access needs by different applications.

False. 우리가 배운 MIPS만 보더라도 displacement mode 하나밖에 없음.

heejongahn / 정리한다
Created Oct 17, 2015
2015 Fall 아키텍쳐 정리
trans_tags = db.Table('trans_tags',
db.Column('history_id', db.Integer, db.ForeignKey('')),
db.Column('tag_id', db.Integer, db.ForeignKey('')),
class TransHistory(db.Model):
id = db.Column(db.Integer, primary_key=True)
datetime = db.Column(db.DateTime)
conductor = db.Column(db.String(20))
tags = db.relationship('TransTag', secondary = 'trans_tags', backref = 'describes')