heejongahn

{"version":1,"resource":"file:///Users/heejong/workspace/flex-landing-page/src/pages-inner/home/TimeTrackingSection/index.tsx","entries":[{"id":"jbwT.tsx","timestamp":1651213027946}]}

heejongahn

# .travis.yml
language: generic

env:
  - FLUTTER_BUILD_RELEASE_CHANNEL=stable # 사용할 빌드 릴리즈 채널

matrix:
  include:
    - name: iOS Build
      os: osx

heejongahn

// Place your key bindings in this file to overwrite the defaults
[
  {
    "key": "cmd+3",
    "command": "editor.action.goToDeclaration",
    "when": "editorHasDefinitionProvider && editorTextFocus && !isInEmbeddedEditor"
  },
  {
    "key": "cmd+4",
    "command": "workbench.action.navigateBack"

heejongahn

import re

from hjlog import db
from hjlog.models import Post

S3_BASE_URL = 'https://s3.ap-northeast-2.amazonaws.com/hjlog-photos/'
pattern = re.compile('!\[(.*)\]\(/static/image/photo/(.*)\)')


def repl(m):

heejongahn

/Users/nobell/workspace/haskell-study/week7/HW07.hs:68:13:
    No instance for (MonadRandom Vector)
      arising from a use of ‘getRandomR’
    In a stmt of a 'do' block: victim <- getRandomR (0, i)
    In the expression:
      do { victim <- getRandomR (0, i);
           (unsafeSwapV i victim v) }
    In an equation for ‘shuffleStep’:
        shuffleStep v i
          = do { victim <- getRandomR (0, i);

heejongahn

configFish <- catchIOError (B.readFile configFishPath)
    (\ e -> if isDoesNotExistError e
        then do
            B.writeFile configFishPath B.empty
            return ""
        else ioError e)

heejongahn

1. Mark whether each of the following statements is true or false.

A. Increasing the block size of a cache always reduces the cache miss rate by increasing the chance to exploit spatial locality. [ T / F ]

False. 블락 사이즈가 너무 커지면 캐시 블락이 몇 개 못 들어가서 miss rate가 높아짐.

B. Increasing the cache size does not reduce coherence misses in shared memory multiprocessors. [T/F]

True. 캐시에 들어있는게 많으니까 invalidation이 늘어남.

C. Increasing the block size does not increase coherence misses in shared memory multiprocessors. [ T / F ]

False. 여러 프로세스가 한 블락에 접근할 확률이 높아서져 coherence miss 증가.

heejongahn

1

1-1. The CPI of a single cycle design is always less than or equal to the CPI of a pipelined implementation.

True. singly cycle design 에서 CPI는 무조건 1. 파이프라인에서는 ideally 1, 실제로는 더 커질 수 있음.

1-2. Since RISC can access the memory only through load and store instructions, RISC must support many different addressing modes to satisfy various memory access needs by different applications.

False. 우리가 배운 MIPS만 보더라도 displacement mode 하나밖에 없음.

heejongahn

우하하

heejongahn

trans_tags = db.Table('trans_tags',
     db.Column('history_id', db.Integer, db.ForeignKey('trans_history.id')),
     db.Column('tag_id', db.Integer, db.ForeignKey('trans_tag.id')),
)

class TransHistory(db.Model):
    id = db.Column(db.Integer, primary_key=True)
    datetime = db.Column(db.DateTime)
    conductor = db.Column(db.String(20))
    tags = db.relationship('TransTag', secondary = 'trans_tags', backref = 'describes')