simple generic up counter in two-process method

tp1.vhd

library ieee;
use ieee.std_logic_1164.all;

package gcnt_pkg is

	component gcnt is
		generic (
			w     : integer range 1 to integer'high := 8;
			async : boolean                         := false
		);
		port (
			clr : in  std_logic;
			clk : in  std_logic;
			o   : out std_logic_vector(w-1 downto 0)
		);
	end component gcnt;

end package gcnt_pkg;

package body gcnt_pkg is

end package body gcnt_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gcnt is
	generic (
		w     : integer range 1 to integer'high := 8;
		async : boolean                         := false
	);
	port (
		clr : in  std_logic;
		clk : in  std_logic;
		o   : out std_logic_vector(w-1 downto 0)
	);
begin
end entity gcnt;

architecture tp of gcnt is

	type t is record
		cnt : integer range 0 to 2**w-1;
	end record t;
	constant c : t := (
		cnt => 0
	);
	signal g : t;
	signal r : t := c;

begin

	p_comb : process (r)
		variable v : t := c;
	begin
		if (r.cnt >= 2**w-1) then
			v.cnt := 0;
		else
			v.cnt := r.cnt + 1;
		end if;

		g <= v;

		o <= std_logic_vector(to_unsigned(r.cnt, w));
	end process p_comb;

	g_async : if (async = true) generate
	begin
		p_seq : process (clr, clk)
		begin
			if (clr = '1') then
				r <= c;
			elsif (rising_edge(clk)) then
				r <= g;
			end if;
		end process p_seq;
	end generate g_async;

	g_sync : if (async = false) generate
	begin
		p_seq : process (clk)
		begin
			if (rising_edge(clk)) then
				if (clr = '1') then
					r <= c;
				else
					r <= g;
				end if;
			end if;
		end process p_seq;
	end generate g_sync;

end architecture tp;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gcnt_pkg.all;

entity tp1 is
begin
end entity tp1;

architecture test of tp1 is

	signal clk : std_logic := '0';
	signal clr : std_logic := '1';
	constant clk_period : time := 1.0 ns;
	constant clr_time   : time := 10 * clk_period;

	constant gcnt_w     : integer range 1 to integer'high := 8;
	constant gcnt_async : boolean                         := false;

	type st_t is (idle, run, done);
	type t is record
		st : st_t;
	end record t;
	constant c : t := (
		st => idle
	);
	signal r : t := c;

	type if_t is record
		gcnt_o : std_logic_vector(gcnt_w-1 downto 0);
	end record if_t;
	signal s : if_t;

begin

	p_clk : process
	begin
		w_clk : while (r.st /= done) loop
			clk <= '0'; wait for clk_period / 2;
			clk <= '1'; wait for clk_period / 2;
		end loop w_clk;
		wait;
	end process p_clk;

	p_clr : process
	begin
		clr <= '1'; wait for clr_time;
		clr <= '0'; wait;
	end process p_clr;

	p_stim : process
	begin
		r.st <= idle;
		wait until (clr /= '1');
		wait until (rising_edge(clk));

		r.st <= run;
		wait until (unsigned(s.gcnt_o) = 0);
		wait until (rising_edge(clk));

		r.st <= done;
		wait;
	end process p_stim;

	u_gcnt : gcnt
	generic map (
		w     => gcnt_w,
		async => gcnt_async
	)
	port map (
		clr => clr,
		clk => clk,
		o   => s.gcnt_o
	);

end architecture test;