areia-1 CPU, version 2

gistfile1.txt

AREIA-1
------------

16 registers, 16 bits each,
        0 = always 0
        15 = SP

Memory is treated as little-endian.
Opcode byte: oooooott (o - opcode, t - type of opcode)
l is .b or .w
Opcode formats:
	OP0     00oooo00
	OP1.1   01oooo0l xxxxyyyy ( op(@x,@y) -> @x )
	OP1.2   01oooo1l xxxxyyyy iiiiiiii [iiiiiiii] ( op(@y,#i) -> @x )
	OP2.1   11oooo00 xxxxbbbb aaaaaaaa aaaaaaaa (jmp $baaaa + @x)
	OP2.2   11oooo01 aaaaaaaa aaaaaaaa (jmp $Saaaa (S taken from upper 4 bits of PC))
	OP2.3   11oooo1l aaaaaaaa [aaaaaaaa] (jmp PC_AT_END_OF_OPCODE + (signed)$aa[aa] - CAN CROSS SEGMENT BOUNDARIES.)
	OP3.1   10ooaa00 xxxxyyyy (ld @x, $SS000 + (unsigned int16)@y)
	OP3.2.  10ooaa01 xxxxbbbb aaaaaaaa aaaaaaaa (ld @x, $baaaa)
	OP3.3.  10ooaa10 xxxxyyyy aaaaaaaa (ld @x, $SS000 + (signed int8 converted to unsigned int16)$aa + @y)
	OP3.4.  10ooaa11 xxxxyyyy aaaaaaaa aaaaaaaa (ld @x, $SS000 + (unsigned)$aaaa + @y)

Addressing modes:
	(I really don't know what these are for, but we're not supporting indirect addressing. Use LD/ST. --GM)
	0 - regular
	1 - indirect ( [@y])
	2 - stack (@y + SP)
	3 - indirect stack ([@y + SP[)
	
Opcodes:
	OP0     nop, ret, popf, pushf, cli, sei, hlt, (unused), ss0, ss1, ss2, ss3
	OP1     move, cmp, add, sub, xor, or, and, asl, asr, lsr, rol, ror, rcl, rcr
	OP2     all the jumps
	OP3     ld.b, st.b, ld.w, st.w 

Notes:
	move with @0 as destination is:
		for l=0, move.b SEGMENT, @y
		for l=1, move.b @y, SEGMENT

	SS0/SS1/SS2/SS3 is "set segment 0/1/2/3", which selects the segment used for memory access.
	By convention:
		SS0 is for general access.
		SS1 is for streaming reads.
		SS2 is for streaming writes.
		SS3 is for stack accesses and is explicitly the one used by PUSHF/POPF/RET.

	PC is a full 20 bits, and doesn't use the segment registers.

FLAGS:
    bit     description
---------------------------------------
    0       ZERO (CMP equality)
    1       CARRY (whether carrying a bit, for subtract follow Z80 impl.)
    2       OVERFLOW (add/sub/cmp: if signed overflow occurs; xor/and/or: sum of all bits over GF(2) (parity))
    3       SIGNED (whether >= 0x8000 or >= 0x80 for b)
    4       INTERRUPT (set to 1 to enable)
    5       SEGB0 (1 uses segments 1/3, 0 uses segments 0/2)
    6       SEGB1 (1 uses segments 2/3, 0 uses segments 0/1)
    7-15    Reserved.