View rc2014.md
View stage1.asm
0000 blport: equ 0H
0000 org 0H
0000
0000 21 07 00 ld hl, stage2
0003 4c ld c, h
0004 44 ld b, h
0005 ed b2 inir
0007 00 stage2: nop
View ROMDump.ino
#define bytesPerLine 16
#define dataSize 131072
#define A16 10
#define _CE 11
#define _OE 12
#define _WE 13
void setupPorts() {
// Set disable writing and output, enable chip
digitalWrite(_WE, HIGH);
View new_ram.v
module ram(clk, addr, data_in, data_out, cs, we);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 8;
parameter INIT_FILE = "";
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output reg [DATA_WIDTH-1:0] data_out;
View test.asm
leds = $D000
dips = $D001
* = $F000
begin lda dips
sta leds
jmp begin
* = $FFFA
View ram.v
module ram(clk, addr, data_in, data_out, cs, we);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 8;
parameter INIT_FILE = "";
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
View cpu_tb.v
module cpu_tb;
reg clk;
reg reset;
reg irq;
reg nmi;
reg rdy;
wire [15:0] addr;
wire [7:0] cpu_do;
View ddt4.txt
103B
C
100G
lu2+1) 654300 ~ el I/ 70 ~ h P
hlu2+1) 430000 ~ l I/ 7065 ~ he P
elu2+1) 0 ~ I/ 706543 ~ hel P
llu2+1) 463300 ~ o, I/ 43 ~ l P
llu2+1) 330000 ~ , I/ 4346 ~ lo P
olu2+1) 0 B
P
View ddt3.txt
Simulation stopped, PC: 006023 (SZF1 I)
sim> att ptr hello.sym
sim> cont
T
100/ lac i ptr
lup+1/ cli
lu2/ rcl 77
lu2+1/ tyo
lu2+2/ sza
lu2+3/ jmp lu2
View ddt2.txt
Simulation stopped, PC: 006024 (JMP 6023)
sim> att ptr hello.rim
sim> cont
Y
100/ lac i 112
101/ cli
102/ rcl 77
103/ tyo
104/ sza
105/ jmp 102