Block ram

ram.v

module ram(clk, addr, data_in, data_out, cs, we);
 
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 8;
parameter INIT_FILE = "";

input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
input cs;
input we;

reg [DATA_WIDTH-1:0] mem[(1 << ADDR_WIDTH)-1:0];

initial
begin
	if (INIT_FILE != "") begin
		$readmemh(INIT_FILE, mem);
	end
end

reg [ADDR_WIDTH-1:0] addr_reg;

always @(posedge clk)
begin
	if (we)
		mem[addr] <= data_in;

	addr_reg <= addr;
end

assign data_out = (cs && !we) ? mem[addr_reg] : 8'bz;

endmodule