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@josyb
Created March 26, 2015 13:56
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Guy Eschemann: TypeError: Unexpected type
from myhdl import *
def mpegChannel(clk, rst, s_tx_data_xor_mask_r):
# table = tuple([9,8,7,6])
@always_seq(clk.posedge, reset=rst)
def fsm_seq():
for i in range(4):
# s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = table[i]
s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = i
# if i == 0:
# s_tx_data_xor_mask_r.next[1 + 7:0] = 0
# elif i == 1:
# s_tx_data_xor_mask_r.next[1 + 15:8] = 1
# elif i == 2:
# s_tx_data_xor_mask_r.next[1 + 23:16] = 2
# else:
# s_tx_data_xor_mask_r.next[1 + 31:24] = 3
return instances()
if __name__ == "__main__":
clk = Signal(bool(0))
rst = ResetSignal(0, active=1, async=True)
s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])
toVerilog(mpegChannel, clk, rst, s_tx_data_xor_mask_r)
toVHDL.numeric_ports = False
toVHDL(mpegChannel, clk, rst, s_tx_data_xor_mask_r)
@freddyowusu31
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hello guy toVerilog(mpegChannel, clk, rst, s_tx_data_xor_mask_r)
toVHDL.numeric_ports = False
toVHDL(mpegChannel, clk, rst, s_tx_data_xor_mask_r)

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