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@josyb
Last active August 29, 2015 14:24
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'''
Created on 27 Mar 2015
@author: Josy
'''
import os
from myhdl import *
class FramedOutput( object ):
''' an interface/record with conversion routines '''
def __init__(self, NBR_OF_TAPS = 16, WIDTH_PIXEL = 10):
self.NBR_OF_TAPS = NBR_OF_TAPS
self.WIDTH_PIXEL = WIDTH_PIXEL
self.data = [Signal(intbv(0)[self.WIDTH_PIXEL:])for _ in range(self.NBR_OF_TAPS) ]
self.startofframe = Signal(bool(0))
self.startofline = Signal(bool(0))
self.endofline = Signal(bool(0))
self.endofframe = Signal(bool(0))
def torecord(self, v):
''' we 'reformat' a vector into an interface/record '''
trWIDTH_PIXEL = self.WIDTH_PIXEL
trNBR_OF_TAPS = self.NBR_OF_TAPS
@always_comb
def torecord():
for i in range(trNBR_OF_TAPS):
self.data[i].next = v[(i+1) * trWIDTH_PIXEL : i * trWIDTH_PIXEL]
self.startofframe.next = v[trNBR_OF_TAPS * trWIDTH_PIXEL+0]
self.startofline.next = v[trNBR_OF_TAPS * trWIDTH_PIXEL+1]
self.endofline.next = v[trNBR_OF_TAPS * trWIDTH_PIXEL+2]
self.endofframe.next = v[trNBR_OF_TAPS * trWIDTH_PIXEL+3]
return torecord
def siml( D , Y):
def op(l1,l2,l3,l4, Y):
''' a dummy operation '''
@always_comb
def op():
ly = 1
for i in range(4):
ly = ly and (l1[i] == l2[i]) and (l3[i] == l4[i])
Y.next = ly
return op
fo = FramedOutput( 16, 4 )
cv = fo.torecord(D)
if USE_LIST:
# l1 = [ fo.data[0+i*4] for i in range(4)]
l1 = [ fo.data[0+i*4](4,0) for i in range(4)]
# l1 = [ fo.data[0+i*4]() for i in range(4)]
l2 = [ fo.data[1+i*4](4,0) for i in range(4)]
l3 = [ fo.data[2+i*4](4,0) for i in range(4)]
l4 = [ fo.data[3+i*4](4,0) for i in range(4)]
else:
l1 = [Signal(intbv(0)[4:]) for _ in range(4)]
l2 = [Signal(intbv(0)[4:]) for _ in range(4)]
l3 = [Signal(intbv(0)[4:]) for _ in range(4)]
l4 = [Signal(intbv(0)[4:]) for _ in range(4)]
@always_comb
def assignl():
for i in range(4):
l1[i].next = fo.data[0+i*4]
l2[i].next = fo.data[1+i*4]
l3[i].next = fo.data[2+i*4]
l4[i].next = fo.data[3+i*4]
el = op(l1, l2, l3, l4, Y)
return instances()
def tb_siml():
D = Signal(intbv(0)[16*4+4:])
Y = Signal(bool(0))
dut = siml(D, Y)
@instance
def stimulus():
D.next = 1234567
yield delay(10)
D.next = 2**(16*4)-1
yield delay(10)
raise StopSimulation
return dut, stimulus
def convert():
D = Signal(intbv(0)[16*4+4:])
Y = Signal(bool(0))
toVHDL(siml, D, Y)
if __name__ == '__main__':
def simulate(timesteps, mainclass):
"""Runs simulation for MyHDL Class"""
# Remove old .vcd file, otherwise we get a list of renamed .vcd files lingering about
filename = (mainclass.__name__ +".vcd")
if os.access(filename, os.F_OK):
os.unlink(filename)
# Run Simulation
tb = traceSignals(mainclass)
sim = Simulation(tb)
sim.run(timesteps)
USE_LIST = True
simulate( 100 , tb_siml)
convert()
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