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@josyb
Last active September 19, 2015 08:04
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another small test to demonstrate the 'delta' issue
def delta(Clk, Reset, D, Wr, Sel, Q):
r = [Signal( intbv(0)[len(D):]) for _ in range(9)]
@always_seq(Clk.posedge, reset = Reset)
def rtl():
if Wr:
r[0].next = D
r[1].next = r[0]
r[2].next = r[1]
r[3].next = r[2]
r[4].next = r[3]
r[5].next = r[4]
r[6].next = r[5]
r[7].next = r[6]
r[8].next = r[7]
Q.next = r[Sel]
return rtl
def test_delta():
clock = Signal(bool(0))
reset = ResetSignal(0, active=1, async=True)
data_in = Signal(intbv(0)[4:])
wr = Signal(bool(0))
sel = Signal(intbv(0)[4:])
data_out = Signal(intbv(0)[4:])
clkcount = Signal( intbv(0)[8:])
def delta_bench():
tbdut = delta(clock, reset, data_in, wr, sel, data_out)
@always(delay(5))
def tbclk():
clock.next = not clock
if clock:
clkcount.next = clkcount + 1
@instance
def tbstim():
reset.next = reset.active
for _ in range(3):
yield clock.posedge
yield clock.negedge
reset.next = not reset.active
yield clock.posedge
yield delay(2)
wr.next = 1
for ii in range(9):
data_in.next = 9 - ii
yield clock.posedge
yield delay(1)
wr.next = 0
for _ in range(3):
yield clock.posedge
yield delay(2)
sel.next = 8
for _ in range(3):
yield clock.posedge
yield delay(2)
for ii in range(9):
sel.next = ii
yield clock.posedge
yield delay(0) # need this one to get a correct printout that corroborates with the .vcd waveform
print( data_out)
yield delay(2) # to offset the input signals a little, giving a bit of 'hold time'
raise StopSimulation
return tbdut, tbclk, tbstim
Simulation(traceSignals(delta_bench)).run()
if __name__ == '__main__':
# test_array3()
# test_array3f()
test_delta()
'''
Created on 18 Sep 2015
@author: Josy
'''
import myhdl
def dmwe(Clk, Sel, Q):
'''
a minimal-working-example to show the 'issue' of having to add
a delta-delay in the simulation test-bench
'''
c = [i+1 for i in range(4)]
@myhdl.always_seq( Clk.posedge, reset = None)
def rtl():
Q.next = c[Sel]
return rtl
def tb_dmwe():
Clk = myhdl.Signal( bool( 1 ))
Sel = myhdl.Signal( myhdl.intbv(0)[2:] )
Q = myhdl.Signal( myhdl.intbv(0)[4:] )
dut = dmwe(Clk, Sel, Q)
tCK = 10
@myhdl.instance
def genclk():
while True:
Clk.next = 1
yield myhdl.delay(tCK // 2)
Clk.next = 0
yield myhdl.delay(tCK // 2)
@myhdl.instance
def stimulus():
# deliberately point Sel to highest element
Sel.next = 2
for _ in range(3):
yield Clk.posedge
yield myhdl.delay( int(tCK // 4)) # offset the inputs a little
# now access all 4 elements starting with the first
print 'without DELTA_DELAY'
for i in range(4):
Sel.next = i
yield Clk.posedge
print Q ,
yield myhdl.delay( int(tCK // 4))
print
for _ in range(3):
yield Clk.posedge
print 'with DELTA_DELAY '
for i in range(4):
Sel.next = i
yield Clk.posedge
yield myhdl.delay( 0 ) # without this delta-delay we get 4 1 2 3 in stead of 1 2 3 4
assert Q == i + 1
print Q ,
yield myhdl.delay( int(tCK // 4))
yield Clk.posedge
raise myhdl.StopSimulation
return dut, genclk, stimulus
if __name__ == '__main__':
myhdl.Simulation( myhdl.traceSignals( tb_dmwe )).run()
@josyb
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josyb commented Sep 17, 2015

The simulation output is identical for both with and without 'delta delay'
image

@josyb
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josyb commented Sep 19, 2015

I added another MWE test: deltmwe.py. Where I also have to insert a 'delta cycle'. Here too the .vcd output is the same for both scenarios:
image

The result:

without DELTA_DELAY
3 1 2 3
with DELTA_DELAY 
1 2 3 4

Not that this behaviour is present in 0.9-maintenance too.

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