- 数学に関係する tweet を TimeLine 上に投稿する bot です。名の通り大半は高校数学の公式です。
- 内容の誤りや数学的におかしいと思ったらどんどん指摘をください。
- 数式や、その式に関するグラフの画像が付いているものがあります。ご活用ください。(現在調整中)
基本は TeX をベースとし、空白の置き方などのスタイルを python から取り入れてます。
%%% reference : | |
%%% (1) パターン認識と機械学習 | |
%%% (2) http://aidiary.hatenablog.com/entries/2014/01/22 | |
clear all; | |
N = 100; | |
EPS = 0.01; | |
ETA = 0.1; | |
LOOP = 500; |
ns = [128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288,1048576,]; | |
A = [2.50758e+007,1.59102e+008,2.52819e+008,3.58365e+008,4.55699e+008,5.09125e+008,5.50919e+008,5.68417e+008,5.21719e+008,5.85463e+008,5.71442e+008,5.65458e+008,5.44664e+008,4.43185e+008,]; | |
B = [7.44185e+007,7.62636e+007,7.62636e+007,5.67871e+007,7.64215e+007,7.65404e+007,7.62636e+007,7.64809e+007,6.93705e+007,7.63154e+007,7.61604e+007,7.53965e+007,7.46425e+007,5.81409e+007,]; | |
figure(1) | |
h1 = loglog(ns, A, 'ro', ns, B, 'bx'); | |
set(h1, 'MarkerSize', 10); | |
set(gca, 'xtick', [128,1024,8192,65536,1048576], 'XLim', [128, 1048576]); | |
legend('para', 'para', 'location', 'northeast'); |
-- td4.vhd | |
-- This file was auto-generated as a prototype implementation of a module | |
-- created in component editor. It ties off all outputs to ground and | |
-- ignores all inputs. It needs to be edited to make it do something | |
-- useful. | |
-- | |
-- This file will not be automatically regenerated. You should check it in | |
-- to your version control system if you want to keep it. |
Sub Sample1() | |
Dim c As Range | |
Dim val As Variant | |
For Each c In Range("B2:H8") | |
val = c.Value | |
Select Case val | |
Case 0 | |
myColor = xlGray75 |
from random import random, choice, seed | |
MAZE = ( | |
# (1, 1, 1, 1, 1, 1, 1), | |
# (1, 0, 0, 0, 1, 1, 1), | |
# (1, 0, 1, 0, 0, 0, 1), | |
# (1, 0, 1, 1, 0, 1, 1), | |
# (1, 0, 1, 1, 0, 1, 1), | |
# (1, 0, 0, 0, 0, 0, 1), |
#!/bin/sh | |
ghdl -a $HDL_FILE | |
ghdl -a $TEST_BENCH | |
ghdl -r $TB_ENTITY |
library IEEE; | |
use IEEE.std_logic_1164.all; | |
entity top_level is | |
port( | |
A, B : in std_logic := 'X'; | |
C : out std_logic := 'X' | |
); | |
end entity; |
-- reference : http://d.hatena.ne.jp/ranha/20091010/1255161992 | |
module Main where | |
data Id {A : Set} (x : A) : A → Set where | |
refl : Id x x | |
reflexive : (A : Set) → (x : A) → Id x x | |
reflexive A x = refl |
library ieee; | |
use ieee.std_logic_1164.all; | |
use ieee.std_logic_unsigned.all; | |
entity three_input_gate is | |
port ( | |
CK, S, P : in std_logic; | |
Q : out std_logic | |
); | |
end entity; |