Glasgow: Change clock to 48MHz for rev A and B

0001-Change-clock-to-48MHz-for-rev-A-and-B.patch

From c54a028448ccea28d5684123dc1ba608f2fb885b Mon Sep 17 00:00:00 2001
From: Konrad Beckmann <konrad.beckmann@gmail.com>
Date: Sun, 22 Aug 2021 00:18:47 +0200
Subject: [PATCH] Change clock to 48MHz for rev A and B

---
 firmware/fpga.c                     | 3 ++-
 software/glasgow/platform/rev_ab.py | 2 +-
 software/glasgow/target/hardware.py | 6 +++---
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/firmware/fpga.c b/firmware/fpga.c
index 4a1c3e4..b8d3bdc 100644
--- a/firmware/fpga.c
+++ b/firmware/fpga.c
@@ -127,7 +127,8 @@ __endasm;
   switch(glasgow_config.revision) {
     case GLASGOW_REV_A:
     case GLASGOW_REV_B:
-      IFCONFIG |= _IFCLKOE|_IFCFG0|_IFCFG1;
+      // IFCONFIG |= _IFCLKOE|_IFCFG0|_IFCFG1;
+      IFCONFIG |= _IFCLKOE|_3048MHZ|_IFCFG0|_IFCFG1;
       break;
 
     case GLASGOW_REV_C0:
diff --git a/software/glasgow/platform/rev_ab.py b/software/glasgow/platform/rev_ab.py
index 9aae855..b98f0dd 100644
--- a/software/glasgow/platform/rev_ab.py
+++ b/software/glasgow/platform/rev_ab.py
@@ -14,7 +14,7 @@ class GlasgowPlatformRevAB(GlasgowPlatformICE40):
         Resource("clk_fx", 0, Pins("44", dir="i"),
                  Clock(48e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
         Resource("clk_if", 0, Pins("20", dir="i"),
-                 Clock(30e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
+                 Clock(48e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
 
         Resource("fx2", 0,
             Subsignal("sloe",    Pins("6", dir="o")),
diff --git a/software/glasgow/target/hardware.py b/software/glasgow/target/hardware.py
index 65c291f..0105462 100644
--- a/software/glasgow/target/hardware.py
+++ b/software/glasgow/target/hardware.py
@@ -25,7 +25,7 @@ class GlasgowHardwareTarget(Module):
     def __init__(self, revision, multiplexer_cls=None, with_analyzer=False):
         if revision in ("A0", "B0"):
             self.platform = GlasgowPlatformRevAB()
-            self.sys_clk_freq = 30e6
+            self.sys_clk_freq = 48e6
         elif revision in "C0":
             self.platform = GlasgowPlatformRevC0()
             self.sys_clk_freq = 48e6
@@ -86,8 +86,8 @@ class GlasgowHardwareTarget(Module):
 
     def build_plan(self, **kwargs):
         overrides = {
-            "synth_opts": ["-abc9"],
-            "nextpnr_opts": ["--placer", "heap"],
+            "synth_opts": ["-nodffe"],
+            "nextpnr_opts": ["--timing-allow-fail"],
         }
         overrides.update(kwargs)
         return GlasgowBuildPlan(self.platform.prepare(self, **overrides))
-- 
2.33.0

readme.md

Enabling 48MHz clock for Glasgow Rev A and B

To build and upload the firmware:

• git submodule update --init --recursive
• cd vendor/libfx2/firmware && make && cd -
• cd firmware && make && cd -
• glasgow flash --firmware firmware/glasgow.ihex
• glasgow run benchmark