error.log

Warning: Wire top.$verilog_initial_trigger has an unprocessed 'init' attribute.
*** GOWIN Tcl Command Line Console  *** 
add new file: "top.cst"
add new file: "top.sdc"
add new file: "top.vg"
current device: GW1N-1  GW1N-LV1QN48C6/I5
NOTE (PJ2001) : Skip synthesis, because there is only one netlist file in this project
Reading netlist file: "/home/konrad/dev/fpga-projects/gowin/nmigen/build/top.vg"
Parsing netlist file "/home/konrad/dev/fpga-projects/gowin/nmigen/build/top.vg" completed
ERROR  (PA2005) : Port 'led_0__io' could not connect other instance except via a buf which should connect PAD
ERROR  (PA2005) : Port 'led_0__io' could not connect other instance except via a buf which should connect PAD
NOTE  (PA0005) : Processing netlist completed with errors

top.debug.v

/* Automatically generated by nMigen 0.3.dev183+g69ed491. Do not edit. */
/* Generated by Yosys 0.9+3672 (git sha1 872d2ba8, gcc 10.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */

(* \nmigen.hierarchy  = "top.pin_led_0" *)
(* generator = "nMigen" *)
module pin_led_0(led_0__oe, led_0__io, led_0__o);
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:278" *)
  wire \$1 ;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:244" *)
  wire \$3 ;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:252" *)
  wire \$5 ;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
  wire led_0__i;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:243" *)
  wire led_0__i_n;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" *)
  inout led_0__io;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
  input led_0__o;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:251" *)
  wire led_0__o_n;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
  input led_0__oe;
  assign \$1  = ~ (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:278" *) led_0__oe;
  assign \$3  = ~ (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:244" *) led_0__i_n;
  assign \$5  = ~ (* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:252" *) led_0__o;
  IOBUF led_0_0 (
    .I(led_0__o_n),
    .IO(led_0__io),
    .O(led_0__i_n),
    .OEN(\$1 )
  );
  assign led_0__o_n = \$5 ;
  assign led_0__i = \$3 ;
endmodule

(* \nmigen.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "nMigen" *)
module top(led_0__io);
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" *)
  inout led_0__io;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
  wire pin_led_0_led_0__o;
  (* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:143" *)
  wire pin_led_0_led_0__oe;
  pin_led_0 pin_led_0 (
    .led_0__io(led_0__io),
    .led_0__o(pin_led_0_led_0__o),
    .led_0__oe(pin_led_0_led_0__oe)
  );
  assign pin_led_0_led_0__oe = 1'h1;
  assign pin_led_0_led_0__o = 1'h1;
endmodule

top.vg

/* Generated by Yosys 0.9+3672 (git sha1 872d2ba8, gcc 10.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */

/* \nmigen.hierarchy  = "top" */
/* top =  1  */
/* generator = "nMigen" */
module top(led_0__io);
  /* init = 1'h0 */
  wire gen_0_;
  /* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" */
  inout led_0__io;
  /* hdlname = "pin_led_0 led_0__i_n" */
  /* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:243" */
  /* unused_bits = "0" */
  wire \pin_led_0.led_0__i_n ;
  /* hdlname = "pin_led_0 led_0__io" */
  /* src = "/home/konrad/dev/litex/nmigen/nmigen/build/res.py:129" */
  /* unused_bits = "0" */
  wire \pin_led_0.led_0__io ;
  /* hdlname = "pin_led_0 led_0__o_n" */
  /* src = "/home/konrad/dev/litex/nmigen/nmigen/vendor/gowin_gw1n.py:251" */
  wire \pin_led_0.led_0__o_n ;
  /* hdlname = "pin_led_0 led_0_0" */
  IOBUF \pin_led_0.led_0_0  (
    .I(\pin_led_0.led_0__o_n ),
    .IO(led_0__io),
    .O(\pin_led_0.led_0__i_n ),
    .OEN(\pin_led_0.led_0__o_n )
  );
  GND \pin_led_0.led_0__o_n_GND_G  (
    .G(\pin_led_0.led_0__o_n )
  );
  assign gen_0_ = \pin_led_0.led_0__o_n ;
  assign \pin_led_0.led_0__io  = led_0__io;
endmodule