nmigen reset problem

output.txt

Issue: Why is counter2 not reset when reset is toggled?
couter1 counter2
0	0
1	1
2	1
3	2
4	2
0	2
1	3
2	3
3	4
4	4

test.py

from nmigen import *
from nmigen.sim import *

def main():
    print("Issue: Why is counter2 not reset when reset is toggled?")

    m = Module()
    m.domains += ClockDomain("sync")
    m.domains += ClockDomain("second")

    # Create a second clock domain that's half the frequency of sync
    clk_second = ClockSignal("second")
    m.d.sync += [
        clk_second.eq(~clk_second)
    ]

    counter1 = Signal(16)
    m.d.sync += counter1.eq(counter1 + 1)

    counter2 = Signal(16)
    m.d.second += counter2.eq(counter2 + 1)

    # Tie a reset signal to both clock domains
    reset = Signal()
    m.d.comb += ResetSignal(domain="sync").eq(reset)
    m.d.comb += ResetSignal(domain="second").eq(reset)

    sim = Simulator(m)
    sim.add_clock(1e-6)

    print("couter1 counter2")
    def process():
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")

        yield reset.eq(1)
        yield Tick(); yield Delay(1e-8)
        yield Tick(); yield Delay(1e-8)
        yield Tick(); yield Delay(1e-8)
        yield Tick(); yield Delay(1e-8)
        yield reset.eq(0)
        print(f"{(yield counter1)}\t{(yield counter2)}")

        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
        print(f"{(yield counter1)}\t{(yield counter2)}")
        yield Tick(); yield Delay(1e-8)
    sim.add_process(process)
    with sim.write_vcd("test.vcd"):
        sim.run()

if __name__ == '__main__':
    main()