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nmigen -> openlane example
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from nmigen.build import * | |
from nmigen.vendor.open_lane import * | |
class sky130_fd_sc_hd(OpenLANEPlatform): | |
openlane_root = environ['OPENLANE_ROOT'] | |
pdk = "sky130A" | |
cell_library = "sky130_fd_sc_hd" | |
settings = { | |
"PL_TARGET_DENSITY": 0.75, | |
"FP_HORIZONTAL_HALO": 6, | |
"FP_VERTICAL_HALO": 6, | |
"FP_CORE_UTIL": 5, | |
} | |
connectors = [] | |
resources = [] | |
class inv(Elaboratable): | |
def __init__(self, width=8): | |
self.i = Signal(width) | |
self.o = Signal(width) | |
def elaborate(self, platform): | |
m = Module() | |
m.d.comb += self.o.eq(~self.i) | |
return m | |
def get_ports(self): | |
return [self.i, self.o] | |
if __name__ == "__main__": | |
platform = sky130_fd_sc_hd() | |
inverter = inv() | |
platform.build(inverter, name="inverter", ports=inverter.get_ports()) |
Like I said, it's a huge WIP, It needs a lot of work on some things and there is a lot of things that need to be considered, so it's not quite as simple as just throwing a POR and OSC in it.
Anyway, this discussion should be moved away from this gist and over to the fork.
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awesome! will give it a try soon. since it emits verilog, why doesn't synchronous logic work? looks like the
create_missing_domain
needs to be fleshed out with a proper por and oscillator?