New pac design

pac1.txt

## -- modules --
axi // bus
uart
spi
i2c
usb
radio

## -- structs --
McuSystem { uart: &'static Uart, }
MediaSystem
NpuSystem
WirelessSystem

## -- enumerations -- 
DmaEnable
HasOverflow
HasUnderflow
InterruptState
InterruptEnable
InterruptMask

# - module: uart
## -- modules
auto_baudrate
bit_period
bus_state

## -- structs
Uart { #[repr(C)], auto_baudrate: ReadWrite<AutoBaudrate>, _reserved1: [u8; 1024], ... }

## -- enumerations

# - module: uart::bus_state
## -- modules

## -- structs
BusState; impl AxiRead<BusState> { fn transmit_busy(&self) -> ReadField<TransmitBusy> , fn receive_busy ...}
    impl AxiWrite<BusState> { fn transmit_busy(self) -> WriteField<TransmitBusy> }
TransmitBusy; impl ReadField<TransmitBusy> { fn bit_is_set(&self) -> BusBusy };
    impl WriteField<TransmitBusy> { fn set_bit(self) -> AxiWrite<BusState> }

## -- enumerations
BusBusy

# bus; - module: axi
## -- structs
ReadWrite<T> { value: u32, _state: T, fn read() -> AxiRead<T> , fn write() -> AxiWrite<T> }
ReadOnly<T> { value: u32, _state: T, fn read() -> AxiRead<T> }
WriteOnly<T> { value: u32, _state: T, fn write() -> AxiWrite<T> }
AxiRead<T>
AxiWrite<T>
ReadField<T>
WriteField<T>

# - module: plic
_either_
Plic<const T: usize, const O: usize, ...> { #[repr(C)],  }
_or_
pub type Plic = plic::Plic<16, 4>;