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Created September 10, 2023 11:35
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Apple TSO
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tso.md

ARM defines ACTLR_EL[321] as implementation defined.

Apple adds an IMPDEF ACTLR_EL12 as s3_6_c15_c14_6 and effectively implements VHE semantics. This does not seem to violate the architecture, since the register contents are IMPDEF anyway so nothing says they can't alias ACTLR_EL1 and ACTLR_EL2 together in EL2.

ACTLR_EL1 is trapped by HCR_EL2.TACR. It is also trapped by HACR_EL2<0> (which has all the controls for fine-grained Apple IMPDEF stuff).

In addition, AIDR_EL1 contains feature bits for Apple IMPDEF functionality. It is identical in EL1 and EL2 and is trapped by HCR_EL2.TID1 and HACR_EL2<4>.

TSO

ACTLR_ELx<1> enables TSO mode. AIDR_EL1<9> indicates that this is supported. In EL2, ACTLR_EL1 redirects to ACTLR_EL2 and therefore this all works with EL2 host without special codepaths. ACTLR_EL2 is effective in EL2. In EL1, ACTLR_EL1 is effective (which is a distinct register, accessed as ACTLR_EL12 from EL2).

So basically this all works "as you would expect" for a VHE style register implementation, it's just that the EL12 variant is IMPDEF because the architecture does not define this register as having those semantics officially.

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