bad adder

half_adder.v

module half_adder(
    input clk,
    a,
    b,
    output reg [0:0] sum,
    carry
);
    always @(posedge clk)
        begin
            sum <= a ^ b;
            carry <= a & b;
        end
endmodule

module test_half_adder;
    reg clk = 0;
    always #1 clk = !clk;

    wire a = 0,
         b = 1;
    wire [0:0] sum = 0,
               carry = 0;

    half_adder ha(clk, a, b, sum, carry);

    initial
        $monitor(
            "Time: %t, clk: %0d, a: %0d, b: %0d, sum: %0d, carry: %0d",
            $time,
            clk,
            a,
            b,
            sum,
            carry
        );
endmodule

Specifically wires are not variables and must have drivers. For variables (reg, log, bit, etc.) you can do this, but wires create drives and when the drivers do not match and the strengths are the same you get an undefined value as the result. The declaration assignment create one continuous driver and the port connection for the half adder creates a second. When these two driver do not match you get an undefined value.