mikea

L1 cache reference                  0.5 ns
Branch mispredict                   5 ns
L2 cache reference                  7 ns                      14x L1 cache
Mutex lock/unlock                   25 ns                     
Main memory reference               100 ns                    4x mutex op, 20x L2 cache, 200x L1 cache
Compress 1K bytes with Zippy        3,000 ns
Send 2K bytes over 1 Gbps network   20,000 ns
Read 1 MB sequentially from memory  250,000 ns

hellerbarde

Latency numbers every programmer should know

L1 cache reference ......................... 0.5 ns
Branch mispredict ............................ 5 ns
L2 cache reference ........................... 7 ns
Mutex lock/unlock ........................... 25 ns
Main memory reference ...................... 100 ns             
Compress 1K bytes with Zippy ............. 3,000 ns  =   3 µs
Send 2K bytes over 1 Gbps network ....... 20,000 ns  =  20 µs
SSD random read ........................ 150,000 ns  = 150 µs

Read 1 MB sequentially from memory ..... 250,000 ns = 250 µs

marianposaceanu

CPU

• L1 cache reference 0.5 ns
• Branch mispredict 5 ns (on a bad CPU architecture you're pretty much screwed)
• L2 cache reference 7 ns
• Mutex lock/unlock 25 ns
• Main memory reference 100 ns
• Compress 1K bytes with Zippy 3,000 ns
• Send 2K bytes over 1 Gbps network 20,000 ns
• Read 1 MB sequentially from memory 250,000 ns

jboner

Latency Comparison Numbers (~2012)
----------------------------------
L1 cache reference                           0.5 ns
Branch mispredict                            5   ns
L2 cache reference                           7   ns                      14x L1 cache
Mutex lock/unlock                           25   ns
Main memory reference                      100   ns                      20x L2 cache, 200x L1 cache
Compress 1K bytes with Zippy             3,000   ns        3 us
Send 1K bytes over 1 Gbps network       10,000   ns       10 us
Read 4K randomly from SSD*             150,000   ns      150 us          ~1GB/sec SSD