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@miyo
Created May 25, 2020
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PYNQ を使って Python で手軽に FPGA を活用 (5) のコードスニペット
`default_nettype none
module bram_copy
(
input wire clk,
input wire resetn,
output wire clk_0,
output wire rst_0,
output wire en_0,
output reg [31:0] addr_0,
output wire [31:0] data_0,
output wire [3:0] we_0,
input wire [31:0] q_0,
output wire clk_1,
output wire rst_1,
output wire en_1,
output reg [31:0] addr_1,
output wire [31:0] data_1,
output reg [3:0] we_1,
input wire [31:0] q_1,
input wire [31:0] ctrl,
output reg [31:0] status
);
assign clk_0 = clk;
assign rst_0 = 1'b0;
assign en_0 = 1'b1;
assign we_0 = 4'h0;
assign clk_1 = clk;
assign rst_1 = 1'b0;
assign en_1 = 1'b1;
reg [31:0] counter;
reg [31:0] addr_1_pre;
reg [3:0] we_1_pre;
reg [31:0] ctrl_reg;
assign data_1 = q_0;
always @(posedge clk) begin
if(resetn == 0) begin
status <= 0;
counter <= 0;
we_1 <= 4'h0;
we_1_pre <= 4'h0;
ctrl_reg <= 32'd0;
end else begin
status <= counter;
ctrl_reg <= ctrl;
if(counter < 128) begin
counter <= counter + 1;
we_1_pre <= 4'hF;
end else begin
we_1_pre <= 4'h0;
if(ctrl_reg == 0 && ctrl != 0) begin
counter <= 0;
end
end
// set source memory address
addr_0 <= {counter[29:0], 2'b00};
// set dist. memory address (wait for RAM 1-latency)
addr_1_pre <= {counter[29:0], 2'b00};
addr_1 <= addr_1_pre;
we_1 <= we_1_pre;
end
end
endmodule // bram_copy
`default_nettype wire
`default_nettype none
module stream_double
(
input wire clk,
input wire resetn,
input wire [31:0] s_tdata,
input wire [3:0] s_tkeep,
input wire s_tlast,
output wire s_tready,
input wire s_tvalid,
output wire [31:0] m_tdata,
output wire [3:0] m_tkeep,
output wire m_tlast,
input wire m_tready,
output wire m_tvalid
);
assign m_tdata = s_tdata * 2;
assign m_tkeep = s_tkeep;
assign m_tlast = s_tlast;
assign s_tready = m_tready;
assign m_tvalid = s_tvalid;
endmodule // stream_double
`default_nettype wire
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