$ wget https://gist.githubusercontent.com/miyo/b36f38354a634d5801b4921423b1b120/raw/fbb97f5d2daf941e5d8a7a9a58bd1091196cdfb2/u-boot.diff
$ git clone git://git.denx.de/u-boot.git
$ cd u-boot
$ git checkout -b v2017.11 refs/tags/v2017.11
$ patch -p1 ../u-boot.diff
$ make ARCH=arm zynq_eclypsez7_defconfig
$ make -j8 ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- all
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# Echo_Server -- | |
# Open the server listening socket | |
# and enter the Tcl event loop | |
# | |
# Arguments: | |
# port The server's port number | |
proc Echo_Server {port} { | |
global terminate | |
set s [socket -server EchoAccept $port] |
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# Echo_Server -- | |
# Open the server listening socket | |
# and enter the Tcl event loop | |
# | |
# Arguments: | |
# port The server's port number | |
proc Echo_Server {port} { | |
global terminate | |
set s [socket -server EchoAccept $port] |
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# Echo_Server -- | |
# Open the server listening socket | |
# and enter the Tcl event loop | |
# | |
# Arguments: | |
# port The server's port number | |
proc Echo_Server {port} { | |
global terminate | |
set s [socket -server EchoAccept $port] |
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require 'nokogiri' | |
xml = Nokogiri::XML($stdin) | |
texts = xml.xpath('//xmlns:text') | |
texts.each{|text| | |
str = "" | |
text.xpath('xmlns:tspan').each{|n| | |
str += n.text | |
} | |
puts str |
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require 'tempfile' | |
class Vivado | |
def self.BUILD; :BUILD; end | |
def self.CONFIG; :CONFIG; end | |
def initialize(dir="prj", name="top", top=nil, kind=Vivado.BUILD) | |
@dir = dir | |
@name = name |
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# THIS IS AN EXAMPLE SCRIPT OF WEB SCRAPING | |
# DO NOT ATACK THE WEB SITE | |
import requests | |
from bs4 import BeautifulSoup | |
import re | |
import sys | |
import urllib | |
if len(sys.argv) < 2: |
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`default_nettype none | |
module bram_to_fifo | |
( | |
input wire CLK, | |
input wire RST, | |
output logic WE, | |
output logic [7:0] DATA_IN, | |
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`default_nettype none | |
module bram_copy | |
( | |
input wire clk, | |
input wire resetn, | |
output wire clk_0, | |
output wire rst_0, | |
output wire en_0, |
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`default_nettype none | |
module bram_example_top ( | |
input wire CLK, | |
input wire RST, | |
output logic DATA_OUT | |
); | |
logic [7:0] DATA_IN; | |
logic WE; |
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