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// SPDX-License-Identifier: GPL-2.0+ OR MIT | |
// | |
// Copyright 2015 Freescale Semiconductor, Inc. | |
// Copyright 2016 Toradex AG | |
#include "imx7s.dtsi" | |
#include <dt-bindings/reset/imx7-reset.h> | |
/ { | |
cpus { | |
cpu0: cpu@0 { | |
clock-frequency = <996000000>; | |
operating-points-v2 = <&cpu0_opp_table>; | |
#cooling-cells = <2>; | |
nvmem-cells = <&fuse_grade>; | |
nvmem-cell-names = "speed_grade"; | |
}; | |
cpu1: cpu@1 { | |
compatible = "arm,cortex-a7"; | |
device_type = "cpu"; | |
reg = <1>; | |
clock-frequency = <996000000>; | |
operating-points-v2 = <&cpu0_opp_table>; | |
#cooling-cells = <2>; | |
}; | |
}; | |
timer { | |
compatible = "arm,armv7-timer"; | |
interrupt-parent = <&intc>; | |
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
}; | |
cpu0_opp_table: opp-table { | |
compatible = "operating-points-v2"; | |
opp-shared; | |
opp-792000000 { | |
opp-hz = /bits/ 64 <792000000>; | |
opp-microvolt = <1000000>; | |
clock-latency-ns = <150000>; | |
opp-supported-hw = <0xd>, <0x7>; | |
opp-suspend; | |
}; | |
opp-996000000 { | |
opp-hz = /bits/ 64 <996000000>; | |
opp-microvolt = <1100000>; | |
clock-latency-ns = <150000>; | |
opp-supported-hw = <0xc>, <0x7>; | |
opp-suspend; | |
}; | |
opp-1200000000 { | |
opp-hz = /bits/ 64 <1200000000>; | |
opp-microvolt = <1225000>; | |
clock-latency-ns = <150000>; | |
opp-supported-hw = <0x8>, <0x3>; | |
opp-suspend; | |
}; | |
}; | |
usbphynop2: usbphynop2 { | |
compatible = "usb-nop-xceiv"; | |
clocks = <&clks IMX7D_USB_PHY2_CLK>; | |
clock-names = "main_clk"; | |
#phy-cells = <0>; | |
}; | |
soc { | |
busfreq { | |
compatible = "fsl,imx_busfreq"; | |
fsl,max_ddr_freq = <533000000>; | |
clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, | |
<&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, | |
<&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, | |
<&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, | |
<&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, | |
<&clks IMX7D_AHB_CHANNEL_ROOT_DIV>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; | |
clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", | |
"dram_alt_sel", "pll_dram", "dram_alt_root", "pfd2_270m", | |
"pfd1_332m", "ahb", "axi"; | |
interrupts = <0 112 0x04>, <0 113 0x04>; | |
interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; | |
}; | |
ocrams_ddr: sram@900000 { | |
compatible = "fsl,ddr-lpm-sram"; | |
reg = <0x900000 0x1000>; | |
clocks = <&clks IMX7D_OCRAM_CLK>; | |
}; | |
ocram: sram@901000 { | |
compatible = "mmio-sram"; | |
reg = <0x901000 0x1f000>; | |
clocks = <&clks IMX7D_OCRAM_CLK>; | |
}; | |
ocrams: sram@180000 { | |
compatible = "fsl,lpm-sram"; | |
reg = <0x180000 0x8000>; | |
clocks = <&clks IMX7D_OCRAM_S_CLK>; | |
status = "disabled"; | |
}; | |
ocram_optee { | |
compatible = "fsl,optee-lpm-sram"; | |
reg = <0x180000 0x8000>; | |
overw_reg = <&ocrams_ddr 0x904000 0x1000>, | |
<&ocram 0x905000 0x1b000>, | |
<&ocrams 0x900000 0x4000>; | |
overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>; | |
}; | |
ocrams_mf: sram-mf@900000 { | |
compatible = "fsl,mega-fast-sram"; | |
reg = <0x900000 0x20000>; | |
clocks = <&clks IMX7D_OCRAM_CLK>; | |
}; | |
etm@3007d000 { | |
compatible = "arm,coresight-etm3x", "arm,primecell"; | |
reg = <0x3007d000 0x1000>; | |
/* | |
* System will hang if added nosmp in kernel command line | |
* without arm,primecell-periphid because amba bus try to | |
* read id and core1 power off at this time. | |
*/ | |
arm,primecell-periphid = <0xbb956>; | |
cpu = <&cpu1>; | |
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; | |
clock-names = "apb_pclk"; | |
out-ports { | |
port { | |
etm1_out_port: endpoint { | |
remote-endpoint = <&ca_funnel_in_port1>; | |
}; | |
}; | |
}; | |
}; | |
intc: interrupt-controller@31001000 { | |
compatible = "arm,cortex-a7-gic"; | |
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
#interrupt-cells = <3>; | |
interrupt-controller; | |
interrupt-parent = <&intc>; | |
reg = <0x31001000 0x1000>, | |
<0x31002000 0x2000>, | |
<0x31004000 0x2000>, | |
<0x31006000 0x2000>; | |
}; | |
}; | |
}; | |
/delete-node/&csi; | |
/delete-node/&video_mux; | |
&aips2 { | |
pcie_phy: pcie-phy@306d0000 { | |
compatible = "fsl,imx7d-pcie-phy"; | |
reg = <0x306d0000 0x10000>; | |
status = "disabled"; | |
}; | |
system_counter_rd: system-counter-rd@306a0000 { | |
compatible = "fsl,imx7d-system-counter-rd"; | |
reg = <0x306a0000 0x10000>; | |
status = "disabled"; | |
}; | |
system_counter_cmp: system-counter-cmp@306b0000 { | |
compatible = "fsl,imx7d-system-counter-cmp"; | |
reg = <0x306b0000 0x10000>; | |
status = "disabled"; | |
}; | |
system_counter_ctrl: system-counter-ctrl@306c0000 { | |
compatible = "fsl,imx7d-system-counter-ctrl"; | |
reg = <0x306c0000 0x10000>; | |
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
status = "disabled"; | |
}; | |
epdc: epdc@306f0000 { | |
compatible = "fsl,imx7d-epdc"; | |
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
reg = <0x306f0000 0x10000>; | |
clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>, | |
<&clks IMX7D_CLK_DUMMY>; | |
clock-names = "epdc_axi", "epdc_pix", "epdc_ahb"; | |
epdc-ram = <&gpr 0x4 30>; | |
qos = <&qosc>; | |
status = "disabled"; | |
}; | |
epxp: epxp@30700000 { | |
compatible = "fsl,imx7d-pxp-dma"; | |
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
reg = <0x30700000 0x10000>; | |
clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; | |
clock-names = "pxp_ipg", "pxp_axi"; | |
status = "disabled"; | |
}; | |
csi1: csi1@30710000 { | |
compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; | |
reg = <0x30710000 0x10000>; | |
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_CLK_DUMMY>, | |
<&clks IMX7D_CSI_MCLK_ROOT_CLK>, | |
<&clks IMX7D_CLK_DUMMY>; | |
clock-names = "disp-axi", "csi_mclk", "disp_dcic"; | |
status = "disabled"; | |
}; | |
mipi_csi: mipi-csi@30750000 { | |
compatible = "fsl,imx7d-mipi-csi"; | |
reg = <0x30750000 0x10000>; | |
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, | |
<&clks IMX7D_MIPI_DPHY_ROOT_CLK>; | |
clock-names = "mipi_clk", "phy_clk"; | |
mipi-phy-supply = <®_1p0d>; | |
csis-phy-reset = <&src 0x28 2>; | |
bus-width = <4>; | |
status = "disabled"; | |
/delete-node/ port@0; | |
/delete-node/ port@1; | |
}; | |
mipi_dsi: mipi-dsi@30760000 { | |
compatible = "fsl,imx7d-mipi-dsi"; | |
reg = <0x30760000 0x10000>; | |
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, | |
<&clks IMX7D_MIPI_DPHY_ROOT_CLK>; | |
clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; | |
power-domains = <&pgc_mipi_phy>; | |
status = "disabled"; | |
}; | |
qosc: qosc@307f0000 { | |
compatible = "fsl,imx7d-qosc", "syscon"; | |
reg = <0x307f0000 0x4000>; | |
}; | |
}; | |
&aips3 { | |
mu: mu@30aa0000 { | |
compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; | |
reg = <0x30aa0000 0x10000>; | |
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_MU_ROOT_CLK>; | |
clock-names = "mu"; | |
#mbox-cells = <2>; | |
status = "okay"; | |
}; | |
mu_lp: mu_lp@30aa0000 { | |
compatible = "fsl,imx7d-mu-lp", "fsl,imx6sx-mu-lp"; | |
reg = <0x30aa0000 0x10000>; | |
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_MU_ROOT_CLK>; | |
clock-names = "mu"; | |
status = "okay"; | |
}; | |
sema4: sema4@30ac0000 { | |
compatible = "fsl,imx7d-sema4"; | |
reg = <0x30ac0000 0x10000>; | |
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; | |
clock-names = "sema4"; | |
status = "okay"; | |
}; | |
sim1: sim@30b90000 { | |
compatible = "fsl,imx7d-sim"; | |
reg = <0x30b90000 0x10000>; | |
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_SIM1_ROOT_CLK>; | |
clock-names = "sim"; | |
status = "disabled"; | |
}; | |
qspi1: spi@30bb0000 { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
compatible = "fsl,imx7d-qspi"; | |
reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; | |
reg-names = "QuadSPI", "QuadSPI-memory"; | |
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_QSPI_ROOT_CLK>, | |
<&clks IMX7D_QSPI_ROOT_CLK>; | |
clock-names = "qspi_en", "qspi"; | |
status = "disabled"; | |
}; | |
sim2: sim@30ba0000 { | |
compatible = "fsl,imx7d-sim"; | |
reg = <0x30ba0000 0x10000>; | |
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
status = "disabled"; | |
}; | |
usbotg2: usb@30b20000 { | |
compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; | |
reg = <0x30b20000 0x200>; | |
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_USB_CTRL_CLK>; | |
fsl,usbphy = <&usbphynop2>; | |
fsl,usbmisc = <&usbmisc2 0>; | |
phy-clkgate-delay-us = <400>; | |
status = "disabled"; | |
}; | |
usbmisc2: usbmisc@30b20200 { | |
#index-cells = <1>; | |
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; | |
reg = <0x30b20200 0x200>; | |
}; | |
fec2: ethernet@30bf0000 { | |
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; | |
reg = <0x30bf0000 0x10000>; | |
interrupt-names = "int0", "int1", "int2", "pps"; | |
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, | |
<&clks IMX7D_ENET_AXI_ROOT_CLK>, | |
<&clks IMX7D_ENET2_TIME_ROOT_CLK>, | |
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, | |
<&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; | |
clock-names = "ipg", "ahb", "ptp", | |
"enet_clk_ref", "enet_out"; | |
fsl,num-tx-queues = <3>; | |
fsl,num-rx-queues = <3>; | |
fsl,stop-mode = <&gpr 0x10 4>; | |
status = "disabled"; | |
}; | |
pcie: pcie@33800000 { | |
compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; | |
reg = <0x33800000 0x4000>, | |
<0x4ff00000 0x80000>; | |
reg-names = "dbi", "config"; | |
#address-cells = <3>; | |
#size-cells = <2>; | |
device_type = "pci"; | |
bus-range = <0x00 0xff>; | |
ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ | |
0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ | |
num-lanes = <1>; | |
num-viewport = <4>; | |
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
interrupt-names = "msi"; | |
#interrupt-cells = <1>; | |
interrupt-map-mask = <0 0 0 0x7>; | |
/* | |
* Reference manual lists pci irqs incorrectly | |
* Real hardware ordering is same as imx6: D+MSI, C, B, A | |
*/ | |
interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, | |
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, | |
<&clks IMX7D_PCIE_PHY_ROOT_CLK>; | |
clock-names = "pcie", "pcie_bus", "pcie_phy"; | |
assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, | |
<&clks IMX7D_PCIE_PHY_ROOT_SRC>; | |
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, | |
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; | |
fsl,max-link-speed = <2>; | |
power-domains = <&pgc_pcie_phy>; | |
resets = <&src IMX7_RESET_PCIEPHY>, | |
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>, | |
<&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; | |
reset-names = "pciephy", "apps", "turnoff"; | |
fsl,imx7d-pcie-phy = <&pcie_phy>; | |
status = "disabled"; | |
}; | |
pcie_ep: pcie_ep@33800000 { | |
compatible = "fsl,imx7d-pcie-ep"; | |
reg = <0x33800000 0x4000>, <0x40000000 0x10000000>; | |
reg-names = "regs", "addr_space"; | |
num-lanes = <1>; | |
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, | |
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, | |
<&clks IMX7D_PCIE_PHY_ROOT_CLK>; | |
clock-names = "pcie", "pcie_bus", "pcie_phy"; | |
assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, | |
<&clks IMX7D_PCIE_PHY_ROOT_SRC>; | |
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, | |
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; | |
fsl,max-link-speed = <2>; | |
power-domains = <&pgc_pcie_phy>; | |
resets = <&src IMX7_RESET_PCIEPHY>, | |
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>, | |
<&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; | |
reset-names = "pciephy", "apps", "turnoff"; | |
fsl,imx7d-pcie-phy = <&pcie_phy>; | |
num-ib-windows = <4>; | |
num-ob-windows = <4>; | |
status = "disabled"; | |
}; | |
rpmsg: rpmsg{ | |
compatible = "fsl,imx7d-rpmsg"; | |
/* up to now, the following channels are used in imx rpmsg | |
* - tx1/rx1: messages channel. | |
* - general interrupt1: remote proc finish re-init rpmsg stack | |
* when A core is partition reset. | |
*/ | |
mbox-names = "tx", "rx", "rxdb"; | |
mboxes = <&mu 0 1 | |
&mu 1 1 | |
&mu 3 1>; | |
status = "disabled"; | |
}; | |
}; | |
&ca_funnel_in_ports { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
port@1 { | |
reg = <1>; | |
ca_funnel_in_port1: endpoint { | |
remote-endpoint = <&etm1_out_port>; | |
}; | |
}; | |
}; |
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