flash_led.v

top.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/08/01 22:34:37
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    input rst,
    input clk,
    output reg [1:0] led
);

parameter S0 = 4'b0001;
parameter S1 = 4'b0010;
parameter S2 = 4'b0100;
parameter S3 = 4'b1000;

reg  [4:0] cur_state = S0;
reg  [4:0] next_state = S0;

reg [25:0] fsm_cnt = 32'd0;
reg fsm_clk = 1'b0;

// 这个描述状态转移
always@(posedge clk or negedge rst)
begin
    if(!rst)
        begin
            cur_state <= S0;
        end
    else
        cur_state <= next_state;
end

always@(posedge clk or negedge rst)
begin
    if(!rst)
        begin
            fsm_cnt <= 32'd0;
            fsm_clk <= 1'b0; // 不加反而多了一个LUT
        end
     else
        if(fsm_cnt < 32'd2500_0000)
            fsm_cnt <= fsm_cnt + 1'b1;
        else
        begin
            fsm_cnt <= 32'd0;
            fsm_clk <= ~fsm_clk;
        end
end

// 这个描述转移规则
always@(posedge fsm_clk) // 只依赖状态驱动?
begin
    case(cur_state)
        S0: next_state <= S1;
        S1: next_state <= S2;
        S2: next_state <= S3;
        S3: next_state <= S0;
        default next_state <= S0; // 真的有必要吗?为什么.
    endcase
end

always@(posedge clk or negedge rst)
begin
    if(!rst)
        led <= 2'b11;
    else
    case (cur_state)
        S0: led <='b00;
        S1: led <='b01;
        S2: led <='b10;
        S3: led <='b11;
        default:led <= 'b00;
    endcase;
end

endmodule