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nickfox-taterli / Word2Vec.ipynb
Created October 2, 2024 07:18
词的向量表示
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@nickfox-taterli
nickfox-taterli / tinyimagenet.ipynb
Created July 17, 2024 15:06
tinyimagenet like simple train
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@nickfox-taterli
nickfox-taterli / 0001-Add-TaterLi-Custom-Patch-RIoTBoard.diff
Created June 14, 2024 14:03
0001-Add-TaterLi-Custom-Patch-RIoTBoard.diff
diff --git a/arch/arm/dts/imx6dl-riotboard.dts b/arch/arm/dts/imx6dl-riotboard.dts
index e7d9bfbfd0e..e09dc6e410f 100644
--- a/arch/arm/dts/imx6dl-riotboard.dts
+++ b/arch/arm/dts/imx6dl-riotboard.dts
@@ -176,7 +176,7 @@
VDDIO-supply = <&reg_3p3v>;
};
- pmic: pf0100@8 {
+ pmic: pfuze100@8 {
@nickfox-taterli
nickfox-taterli / rtl_bram.v
Created May 3, 2024 12:02
RTL AXI4Lite BRAM
module rtl_bram(
input wire clk,
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
input wire rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31:0] s_axil_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2:0] s_axil_awprot,
@nickfox-taterli
nickfox-taterli / wsram.v
Created April 2, 2024 14:13
wishbone sram
module top(
input [31:0] adr,
input [31:0] dat_w,
output reg [31:0] dat_r,
input [3:0] sel,
input cyc,
input stb,
output reg ack,
input we,
input [2:0] cti,
@nickfox-taterli
nickfox-taterli / spi.v
Created March 23, 2024 13:39
spi slave at tang nano 20k
module top(
input wire clk_i,
input wire rst_i,
input wire sdi_csn_i,
input wire sdi_clk_i,
input wire sdi_dat_i,
output wire sdi_dat_o,
output wire [5:0] led
@nickfox-taterli
nickfox-taterli / bram_axil.v
Last active February 15, 2024 14:01
bram_axil.v
module bram_axil(
input wire clk,
input wire rst,
input wire [31:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvaild,
output wire s_axil_awready,
input wire [31:0] s_axil_wdata,
input wire [3:0] s_axil_wstrb,
@nickfox-taterli
nickfox-taterli / ser_10to1.v
Created January 11, 2024 09:03
Zynq HDMI Output
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/01/08 18:22:57
// Design Name:
// Module Name: ser_10to1
// Project Name:
// Target Devices:
@nickfox-taterli
nickfox-taterli / fsm.v
Created October 19, 2023 10:12
fsm.py to fsm.v - migen default
/* Machine-generated using Migen */
module top(
output reg example,
output reg [7:0] example_1,
output fsm,
output reg fsm_1,
output fsm_2,
output reg fsm_3,
input sys_clk,
input sys_rst
@nickfox-taterli
nickfox-taterli / qmtech_ep4cgx150.v
Created October 13, 2023 11:45
Qmtech EP4CGX150 VexRiscv by Litex Tools
// -----------------------------------------------------------------------------
// Auto-Generated by: __ _ __ _ __
// / / (_) /____ | |/_/
// / /__/ / __/ -_)> <
// /____/_/\__/\__/_/|_|
// Build your hardware, easily!
// https://github.com/enjoy-digital/litex
//
// Filename : qmtech_ep4cgx150.v
// Device : EP4CGX150DF27I7